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GE-115 Emulator
An Emulator of the General Electrics GE-115 computer
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Source: cp06 CHAPTER 002, "VARIANTI E OPZIONI / CHANGE AND OPTION", drawing 140 130 65 6, UCE 460. PDF page 79 of GE 120 CENTRAL PROCESSOR [6].pdf.
The GE-120 is configured by plugging small jumper cards into three backplane connector positions, plus one switch on the maintenance panel. Everything below is on that one sheet.
cp06 CHAPTER 001, "SELEZIONE CAPACITA' MEMORIA / MEMORY CAPABILITY SELECTION", dwg 14013 065 6, PDF page 78 – the sheet immediately before ch.002. Same mechanism, two more connector positions, E05 and F05:
| version | memory | E05 | F05 | VAMA2 | VEMB6 | VAMC2 |
|---|---|---|---|---|---|---|
| UCE 460 | 8K | / | / | 1 | 1 | 1 |
| UCE 461 | 12K | PONT2N | / | 1 | 1 | 0 |
| UCE 462 | 16K | / | PONT2N | 1 | 0 | 1 |
| UCE 463 | 24K | PONT2P | PONT2N | 0 | 0 | 1 |
| UCE 464 | 32K | PONT2N | PONT2P | 0 | 0 | 0 |
The connector blocks: E05 carries VAMC2 on pin 4 and VAMA2 on pin 3; F05 carries VAMA2 on pin 3 and VEMB6 on pin 1. The same S42 "LAMPS" note applies – VAMA1/VAMB1/VAMC1 follow VAMA2/VEMB6/VAMC2 unless S42 is in DIAG, when they become 1 / 0 / 1.
So the UCE numbering runs on two independent axes: 460-464 is the memory capacity (ch.001) and 466-468 is the processor version (ch.002). A machine is one of each.
gemu allocates a flat 64K array (MEM_SIZE in ge.h) but no longer uses it all: since 2026-07-31 the memory phases honour the selection, so the machine has core exactly where its straps say and nowhere else. This machine is strapped 32K — the UCE 464 row — and an address past that raises INV ADD instead of reading or writing. See the note at the end of this file.
Three option connector positions in the backplane, drawn on ch.002 as the four COIN blocks and labelled by position:
| position | selects | signals |
|---|---|---|
| E04 | which two connectors are enabled for the initial LOAD | FUL26, FUL36 |
| F03 | which connectors may raise an interruption | INES3, INES4 |
| F04 | machine version: cycle period and instruction set | FEL06, FEL16, FUL4G |
The jumper cards are **PONT2N** and **PONT2P** – those two types only; "no card fitted" is itself a valid configuration and is what the tables print as /.
Correction, 2026-07-21. Earlier revisions of this file (and of signals.h/ge.c) named a third type, "PONT2H". It does not exist: every "PONT2H" was a misread of PONT2N in the 1968 typewriter face of ch.001/ch.002, re-read at 400 dpi after the physical cards were identified at Electric Dreams: 0618034Z reads PONT2N on the board, and 0618035V is electrically a PONT2N as well (different part code, same strap function). The identification question this file used to pose – "is 0618034Z a PONT2P or a PONT2H?" – was therefore answered neither.
One maintenance panel switch: **S42, labelled "LAMPS"**, whose DIAG position overrides part of the strapping (see the note below).
| version | cycle period | performances | interruptions | E03 | F04 | FEL06 | FEL16 | FUL4G |
|---|---|---|---|---|---|---|---|---|
| UCE 466 | 6 µsec | MIN | no | / | PONT2N | 1 | 1 | 0 |
| UCE 467 | 4 µsec | MAX | no | PONT2P | PONT2P | 0 | 1 | 1 |
| UCE 467 | 4 µsec | MAX | yes | PONT2P | / | 0 | 1 | 1 |
| UCE 468 | 2 µsec | MAX | no | PONT2N | PONT2P | 0 | 0 | 1 |
| UCE 468 | 2 µsec | MAX | yes | PONT2N | / | 0 | 0 | 1 |
So **FUL4G reads "this machine has the MAX instruction set"** — it is 0 only on the slow 6 µsec UCE 466.
| connectors enabled | F03 | INES3 | INES4 |
|---|---|---|---|
| 3 and 4 | / | yes | yes |
| 3 | PONT2N | yes | no |
| 4 | PONT2P | no | yes |
| connectors enabled | E04 | FUL26 | FUL36 |
|---|---|---|---|
| 2 and 3 | / | 1 | 1 |
| 2 and 4 | PONT2N | 1 | 0 |
| 4 and 3 | PONT2P | 0 | 1 |
Printed on ch.002 in both languages:
THE LEVEL OF THE SIGNALS FUL01 - FUL11 - FUL4F IS THE SAME OF THE SIGNALS FEL06 - FEL16 - FUL4G (RESPECTIVELY), WHEN THE SWITCH "LAMPS" (S42 IN THE MAINTENANCE PANEL) IS NOT IN THE POSITION "DIAG". AT THE CONTRARY, WHEN S42 IS IN THE POSITION "DIAG" THE LEVEL OF THE ABOVE MENTIONED SIGNALS BECOMES: FUL01=0 ; FUL11=0 ; FUL4F=1
So each of these has two forms: a G/06/16 form driven by the straps, and an F/01/11 form that the DIAG switch can force. **FUL4F is the one the timing charts cite as {FUL4}.**
The LA, LPSR and register beta sheets carry a row CI89 SET ALTO {FUL4}, and CI89 sets the hardware stop flip-flop. Reading that with the table above: those instructions halt the machine when FUL4 is asserted, and FUL4 is asserted either on a MAX-performance machine or with the maintenance switch in DIAG.
That is worth flagging as an open question rather than a settled reading, because the obvious interpretation runs the wrong way: a MAX machine is the one that should support these instructions. Two possibilities:
{/FUL4}), so the MIN machine halts on an instruction it does not implement – which is exactly what an unimplemented-operation trap looks like on a machine with no trap mechanism; orResolving it needs the LA/LPSR beta sheets re-read at the CI89 row for an overbar. Until then gemu carries the option model but not the row.
Sharpened by the 2026-07-21 identification: on a UCE 468 the strap levels are FEL06/FEL16/FUL4G = 0/0/1 and the DIAG override forces 0/0/1 – identical, so S42 is a no-op for these signals on this machine and FUL4 is asserted unconditionally. There is no switch position in which a verbatim CI89 SET ALTO {FUL4} would NOT halt this machine, which leans further toward the overbar reading.
Its card layout is public: https://docs.google.com/spreadsheets/d/19S23bxF4Ik-H6zl61luwYC_t-KFmUUzMeeC4uNQSRVo/ sheet "Posizione schede su armadio CPU". Rows are listed in pairs (AB, CD, EF, ...), so the option positions are all on the EF line:
card 05: 0618034Z | 0618035V <- row E | row F card 04: (empty) card 03: 0618034Z | 0618035V card 06 and up: 47F 47F 47F 47F 11T 32H ... 44T 44T ...
Two things stand out. The sheet writes the FULL part number only at cards 03 and 05 – every other position is the 3-character suffix (44T "44-tango", 53F, 40V, 47F...) – which marks those two as the option cards rather than part of the ordinary logic population. And card 04 is empty in both rows.
Reading that against the tables:
That F04 reading corrected a bug here: FUL4G had been derived as F04 == PONT2P, which reads TAB.1 off the "no interrupts" rows only and gets an empty F04 backwards. It is low for exactly one strap, F04 = PONT2N.
Read off the machine: E03 carries 0618034Z, which is printed PONT2N, and F03 carries 0618035V, which is electrically a PONT2N too despite the different part code (identified by its trace pattern against the confirmed 2N). Against the tables:
Both part numbers being PONT2N applies at card 05 too (E05 = 34Z, F05 = 35V), so the machine's capacity straps are E05 = N, F05 = N – a combination the ch.001 table never defines. The five printed rows are / / (8K), N / (12K), / N (16K), P N (24K), N P (32K).
RESOLVED (2026-07-21): the per-pin reading wins. Requiring one fixed shorted-pin set per card type to reproduce every printed row of TAB.1, TAB.2, TAB.3 and the ch.001 table simultaneously over-determines the answer:
PONT2N shorts pins {1, 4} PONT2P shorts pins {1, 3}
(and drops the F04 pin assignment out as a bonus: FUL4G on pin 4, the interrupt inhibit on pin 1, explaining why both card types disable interrupts in F04). The trace-side photos of the machine's two cards show identical etch and identical solder patterns, corroborating that both are the same type.
So the machine's N+N at card 05 reads **(VAMA2, VEMB6, VAMC2) = (1, 0, 0)**: VAMA2 is grounded only by a PONT2P, and there is none. That is no printed row. gemu now computes the selection signals from the pin mechanism (signals.h), straps N+N as found, and ge_memory_capacity_k() reports the combination as off-table (0) rather than guessing; the startup log says so explicitly. What the memory bound logic actually does with (1, 0, 0) is the remaining open question – the ch.001 fan-outs point at (077-x)/(309-x)/ (318-x)/(321-x) for the consumers, and a memtest on the machine above 16K would answer it empirically.
What the machine most plausibly IS, under 4x PONT2N (E03/F03/E05/F05 all N, E04/F04 empty): processor fully defined – UCE 468, 2 us, MAX, interruptions on connector 3, load on 2+3. Memory formally undefined, but reading the ch.001 rows as a two-level decode (VAMA2 splits the table, then VEMB6, then VAMC2 only where a choice remains) puts (1,0,0) in the VAMA2=1/VEMB6=0 branch, whose only printed row is 16K with VAMC2 as a don't-care. Circumstantial support: the funktionalcpu memtest sweeps to exactly 0x4000 = 16K and the deck never touches above it.
The strap set also tells a coherent upgrade story: pre-upgrade UCE 467, 4 us, 24K = E03=P, E05=P, F05=N. Upgrading to 468/32K required E03 P->N (done), E05 P->N (done), and F05 N->P – apparently never done. The two pulled P cards would be exactly the two 18036 spares, and the machine would have been running 16K of its intended 32K ever since, invisibly to every deck that stops at 0x4000. To settle: memtest above 0x4000 on the machine; or check whether F05 is actually populated (empty would make it a clean printed 12K row); or trace the VAM consumers (077/309/318/321).
The memory bound is now gate-derived, not inferred: cp06 ch.080 "MEMORY
STARTING LOGIC / LOGICA PARTENZA MEMORIA" (p156) is the functional consumer of the VAM signals – the (309/318/321-x) fan-outs are only termination divider networks, and (077-x) is the diagnostic option. Four NANDs watch address bits 12-14 against VAMA1/VAMB1/VAMC1 and inhibit VAMEA, the memory START, so an out-of-bounds address never begins a cycle. The terms reproduce all five printed rows and define every off-table combination; for this machine's (1,0,0) only the bit14 term is armed: the machine bounds at exactly 16K. DIAG forces (1,0,1) = the same 16K bound regardless of straps – the diagnostic option's ceiling comes from these same gates. Transcribed as ge_mem_in_bounds() / ge_memory_capacity_k().
The three spare cards complete the upgrade story. Photographed spares: two boards stamped 18036 with 5 staples each, one 18034 with a single staple. A pre-upgrade machine of E03=P, F03=P, F05=N, E05=empty (= UCE 467, 4 usec, interrupts on connector 4, 16K) upgraded toward 468 / connector 3 / 32K pulls exactly two P cards (E03, F03) and one N card (F05) – matching the spares two-and-one – and requires fitting a P in F05, where a new-style N went in instead: the single wrong card that leaves the machine at 16K of its intended 32K. Under this story the staple counts are revision differences only (old N = 1 staple, old P = 5, new N = 4).
The strap cards are documented in GE 120 CENTRAL PROCESSOR [10F].pdf, drawing 015 433 91 "PIASTRINE ST S.C.L.1 / PONT A,B,C,D,E,0F,0G,0H,0L,
2,4,8,0M,2N,2P,2Q":
Consequences: the in-machine 4-bridge cards match the catalog 2N recipe in COUNT and in pattern (holes 20-21 = the adjacent pair, 3 and 25 the two singles), which retires the {1,3,4}-union hypothesis – a doctored card would not match the 4-bridge recipe.
Field-confirmed: before the 4x PONT2N, the four option sockets held two PONT 2 and two PONT B. Their catalog networks (dwg 015 433 91 p253):
PONT B: 7-17 only PONT 2: {1,2}-8 3-7 9-16 {4,15}-17
Neither connects pin 1 (ground) to pin 3 or pin 4, the option sockets' signal pins – so IN THESE SOCKETS both cards are electrically EMPTY: placeholder/dust-cover cards that tie commons. The old configuration was therefore, placement-independently, the all-empty decode: FEL06=FEL16=1 (6 usec timing), FUL4G=1 (F04 empty: MAX ops enabled – an off-table CPU row), INES3=INES4=1 (interrupts on both connectors), (VAMA2,VEMB6,VAMC2) = (1,1,1) = the 8K row. The machine ran in base mode: 6 usec, 8K, interrupts everywhere.
And the spares accounting closes exactly: the two 5-staple 18036 spares match PONT 2 (5 normali {1,8,20,33,46}; the "speciale 4B-5A" is the sixth entry, evidently not a staple), the two 1-staple 18034 spares match PONT B (hole 25 alone). Four spares = the four pulled placeholders. No PONT2P ever existed on this machine, and the upgrade was ONE event: fitting the four PONT2Ns – 2 usec/MAX/connector-3 achieved, 32K intended but landed on the off-table N+N = 16K. Sight check: a 18036's staples should sit at holes 1/8/20/33/46 of the p254 diagram; the 18034's single staple at 25.
Buzz-out, now catalog-grounded (one beep decides): pin 1 <-> 4 = PONT2N, pin 1 <-> 3 = PONT2P; the full beep groups are {1,2,4,7,17} vs {1,2,3,7,17}. Identify the spares by laying their bridges over the p254 hole diagram.
The machine has 2x MEM470 mounted, and cp04 s.8.3's build table puts two boxes only on the 24K and 32K builds (one MEM470 = one 128x128 matrix = 16K positions; 8/12/16K ship with a single box). The 24K-vs-32K fork is closed by the read-amplifier population rule (cp01 PDF p308: Q28/Q29 on 24K and 32K, Q30/Q31 only on 32K) read against the machine's own layout sheet: row QR carries EIGHT identical 02J AMPL2A boards at positions 24-31 – Q30 and Q31 included – with the column calibration verified by TEME2A 70Y at 20 and GEMA2A 27D at 13 matching cp08's factory row Q exactly. The machine is a 32K physical build, bounded to 16K by the strap: one PONT2P in F05 (bridge at hole 2 instead of hole 20, dwg 015 433 91 p254) restores the printed {N,P} = 32K row.
gemu is strapped 32K and enforces the bound (2026-07-31): ge_init sets E05 = PONT2N + F05 = PONT2P, the printed {N,P} = UCE 464 row, which is the owner's reading of the boards and agrees with the physical build above; and the memory phases now ask ge_mem_in_bounds() instead of assuming the whole address space, so an address past the strapped capacity raises INV ADD and never cycles memory, exactly as ch.080 has it. 32K itself is the ceiling the gates cannot express – they only decode bits 12-14, because 32K is the top of the ch.001 table – so pulse.c adds it: an address with bit 15 set, which a change register plus displacement can still compute, addresses core no build has and gets the same INV ADD.
This is what funktionalcpu.cap needed. Strapped at the off-table {N,N} = 16K reading, the deck stopped in the memory test at the manual's own 0x1466 "error 8-24K" halt with INV ADD lit – the right answer for a 16K machine, and the wrong machine. At 32K it runs the 0x4000 and 0x6000 memory tests through to report_and_end. ge->mem_size stays as a harness override for tests that want a specific capacity without restrapping; 0 (the default) means "ask the straps". The INIB2A inhibit boards are the 29W cards in row ST (cod 0610029); cp01 p323 s.2.3.17.3 discriminates them from AMPL2A at sight.
One of the machine's strap cards, in hand: an orange single-sided board in a blue carrier, 17-pin gold edge connector – matching cp08's PIEDINI DEL CONNETTORE 01-17 – date-stamped 19 APR 1971. Three findings:
18035, the other 18034 (over-struck), and BOTH are hand-marked "PONT 2N" with 618034 written on – reading as the PONT2N assembly's catalogue number being annotated onto whichever bare board carries it. The stamped numbers are the boards' own part markings, which is where the layout sheet's 0618034Z / 0618035V split comes from. The two cards were pulled from E03 and E05 – both row-E option positions physically confirmed PONT2N – and one of them is the 18035-stamped board, so the layout sheet's per-row stamp assignment is itself approximate. F05 remains unverified (strapped PONT2N on the both-codes-are-2N instruction); the buzz-out is deferred, so the N+N capacity reading stays flagged as open.The F03 card was found and is back (2026-07-21). All four option sockets – E03, F03, E05, F05 – hold the same 4-bridge card type, under two part stamps (18034/18035), all hand-annotated PONT2N.
The annotation may be stale. Bridges can only be ADDED to a board, and a pristine old-revision PONT2N with a single bridge exists in the spares – so a 4-bridge card could be that card plus three later bridges, i.e. NOT a pure N. The concrete rival: **{1,3,4} = N+P union, a "universal" strap card**. A uniform fleet of union cards fits every socket without tracking N-vs-P (which would explain why all four sockets hold the identical type), and reads:
So the buzz-out decides between two different machines:
4-bridge buzzes {1,4} -> 16K bound, interrupts on connector 3,
the F05-blunder story stands
4-bridge buzzes {1,3,4} -> 32K (all of it addressable), no peripheral
interrupts, no blunder -- and gemu's straps
must be updated
One measurement – pin 3 to pin 1 on any in-machine card – splits the tree. gemu models the pure-N reading until then.
The 44-tango (0610044T) is the commonest logic card in the CPU – rows E and F alone hold about a dozen from card 18 upward, including E36 and E37 – and it is a LOSE23/LOSE2S logic board, not a PONT jumper. The option positions are at the other end of the row, cards 03 to 05.
struct ge_options in ge.h holds E04, F03, F04 (as enum ge_pont) and S42_diag. signals.h derives FUL26, FUL36, FUL4G, FUL4F from them, with FUL2/FUL3/FUL4 as the names the charts use. The default – all connectors empty, S42 not in DIAG – is the E04-empty row of TAB.3, which is what the initial-load tests assume.
1.9.8