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GE-115 Emulator
An Emulator of the General Electrics GE-115 computer
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#include <stddef.h>#include <stdlib.h>#include <string.h>#include "ge.h"#include "signals.h"#include "log.h"Go to the source code of this file.
Macros | |
| #define | GE_MAX_CORE 0x8000u /* 32K: the largest build ch.001 defines */ |
| Does the machine have core at this address? | |
Functions | |
| static uint8_t | odd_parity (uint8_t data) |
| Compute the odd-parity bit for an 8-bit data value. | |
| static int | mem_addr_installed (struct ge *ge, uint16_t addr) |
| static void | mem_fault (struct ge *ge, uint8_t *lamp) |
| The fault lamps, and the error stop. | |
| static void | on_TO00 (struct ge *ge) |
| static void | on_TO10 (struct ge *ge) |
| static void | on_TO11 (struct ge *ge) |
| static void | on_TO15 (struct ge *ge) |
| static void | on_TO19 (struct ge *ge) |
| static void | on_TO20 (struct ge *ge) |
| static void | on_TO25 (struct ge *ge) |
| static void | on_TO30 (struct ge *ge) |
| static void | on_TO40 (struct ge *ge) |
| static void | on_TO50 (struct ge *ge) |
| static void | on_TO50_1 (struct ge *ge) |
| static void | on_TO60 (struct ge *ge) |
| static void | on_TO64 (struct ge *ge) |
| static void | on_TO65 (struct ge *ge) |
| static void | on_TO70 (struct ge *ge) |
| static void | on_TO80 (struct ge *ge) |
| static void | on_TO89 (struct ge *ge) |
| static void | on_TO90 (struct ge *ge) |
| static void | on_TI05 (struct ge *ge) |
| static void | on_TI06 (struct ge *ge) |
| static void | on_TI10 (struct ge *ge) |
| void | pulse (struct ge *ge) |
Variables | |
| static on_pulse_cb | pulse_cb [END_OF_STATUS] |
| #define GE_MAX_CORE 0x8000u /* 32K: the largest build ch.001 defines */ |
Does the machine have core at this address?
The answer is the backplane's, not a setting: cp06 ch.080 MEMORY STARTING LOGIC watches address bits 12-14 against the ch.001 capacity straps, and an address past the installed capacity simply never starts a memory cycle (ge_mem_in_bounds, signals.h). This machine is strapped 32K (E05 PONT2N + F05 PONT2P, TAB.1's UCE 464 row), so all of 0x0000-0x7FFF is there.
The 32K ceiling itself is not one of those gates: ch.080 only decodes bits 12-14, because on the largest machine there is no bit 15 of memory to decode – 32K IS the top of the ch.001 table and of the physical build (two MEM470 boxes, 16K positions each). An address with bit 15 set can still be computed, by a change register plus displacement, and it addresses core that no build has; it gets the same INV ADD as any other absent address.
mem_size stays as the harness override for tests that want a specific capacity without restrapping the machine; 0 (the default) means "ask the
straps".
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The fault lamps, and the error stop.
A memory fault does not just light a lamp: it stops the subsystem, which is why CLEAR is "required after MEM CHECK" (CPU[4] §3.3) and why the maintenance panel has a switch to turn the stop off – INAR, "inhibits the error stop on a memory check error or on addressing a non-existent address" (§4.2, fo.35). The lamp is raised either way; only the stop is inhibited.
This is what ends a console storage key-in. With the rotary at position 8 and neither PAPA nor the step switch inserted, nothing stops the machine at the end of a cycle (fo.98's ALSOA=0 exempts position 8 along with NORM), so it goes on storing the AM switches at V1 and advancing V1 – through the whole of core, exactly as the machine at Electric Dreams does – until the address walks off the installed memory and INV ADD sets ALTO. Insert PAPA and each START stores one byte instead.
The LAMP is a condition, not a latch: it reports the memory cycle you are looking at, and a good cycle puts it out again. That is only visible with the stop inhibited – INAR in, nothing loaded, START: the machine walks zeroes up through core, and INV ADD comes on as the addresser passes the installed memory and goes off again as it wraps to 0, blinking once per lap. Observed on the restored machine, 2026-07-31. With INAR out the machine stops ON the faulting cycle, so the lamp stands there lit, which is the other half of the same behaviour – and why CLEAR is "required after MEM CHECK": what CLEAR releases is the stop.
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