The entire state of the emulated system, including registers, memory, peripherals and timings.
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The entire state of the emulated system, including registers, memory, peripherals and timings.
Definition at line 94 of file ge.h.
Recycle delay line.
Initially is set by "CLEAR", after that it is reset cyclicly. The reset pulse is TO10, the normal setting pulse is TO90 if a LOLL instruction has not been performed, in this case it is set by TI05, with a delay of about 130ns. (cpu fo. 96).
NOTE: documentation differs at cpu fo. 99 that states:
The ACIC1 FF is reset by the TO10 pulse and it is set by the TO901 with the condition PODIB == 1.
PODI is the FF which stores the LOLL diagnostic instruction performance causing an increase of the cycle of about 130 ns.
In fact, if PODIB == 0 the recycling occurs with the pulse TI05 instead of TO90.
Definition at line 298 of file ge.h.
Jump Condition Verified.
Reset in the E0 status of the alpha phase, together with AINI, with the CI39 command (cpu fo. 96).
Set in the E6 status of the alpha phase of the jump instructions (CI38) if signal DC16 (verified condition) is present (cpu fo. 96).
Definition at line 319 of file ge.h.
Selection Channel 1.
Used during the general B phase for command forwarding or condition examination. Unconditionally set by command CE02 which enables the channel selection even if the interested channels are 2 or 3. When a character transfer in output has been initiated with channel 1, signal PAP4A resets PUC1 at the start of the transper phase, when the first transfer is done from RO in to RA (CE00) unless signal PAR21 had already absolved this function. (cpu fo. 235).
Note: the above GE docs refers to PUC2, however in intermediate block diagram fo. 10, it's shown the real flipflop is PIC1, and PUC2 is derived combinatorially from it.
Definition at line 360 of file ge.h.
Asynchronous Channel 1 Cycle Request.
It is set with the OR of the channel 1 request triggers (RAI01) if the executing instruction is not over (RIVEF=1). Also, when the SITE key is inserted during a during a transfer of channel 1 (RAISI2=1). It is reset during a cycle of channel 1 with CE18 (enable RIAP), or at the end of a transfer on channel 1 (cpu fo. 114)
Definition at line 420 of file ge.h.
Asynchronous Channel 2 Cycle Request.
It is set with the trigger LU08 from the integrated reader, or when the SITE key is inserted (RAITI1=1) during the transfers on channel 2.
Request from printer do not act on RC02, but are derived from it with an OR (RIMZA).
It is reset during a cycle of channel 2 with CE18 (enable RIAP), or at the end of a transfer on channel 2 (cpu fo. 114).
Definition at line 435 of file ge.h.
Asynchronous Channel 3 Cycle Request.
It is set with the OR of the cycle request triggers relative to channel 3 (RA301=1) if the executing instruction is not over (RIVAF=1) and additional performances of the GE-130 are enabled (FUL4F=1).
It is reset during a cycle of channel 3 with CE18 (enable RIAP), also, it is reset when the SITE key is inserted (RAITI=1) during a data transfer on channel 3 (RES36=1), or at the end of transfer on channel 3 (PIC32=0) (cpu fo. 114).
Definition at line 450 of file ge.h.
Synchronous CPU Cycle Request.
Is conditioned by the signals ALTOF and RAM02.
When the FF ALTOF is reset, the cycle requests from the CPU are not serverd, therefore the internal calculation is stopped. This counter consists of the FF RAMO and RAMI and counts with the pulse TO10.
Definition at line 462 of file ge.h.
Peripheral unit sequencer.
4-bit sequencer used for data xechange with peripheral units through channel 2.
Drives the NA knot when the cycle has been attributed to channel 2.
Loaded with the first 4 bits of the future status network
- after the execution of a channel 2 cycle
- when forcing a status in SI using CU20 (DC status of general beta phase)
Definition at line 210 of file ge.h.
Main sequencer.
Drives the NA knot when the cycle has been attributed to the CPU or channel 1.
It is used to establish the sequence for:
- alpha phase for all internal and external instructions
- beta phase of internal instructions
- organisation phase (general beta) of external instructions
- program loading
Loaded from the future status network when signal SOC01 is activated, provided the RICI key is not active, in the following cases:
- the FF ARES has been set thru "CLEAR". This causes the machine to execute the status 00, and setting of SO07 using CU07, this will set the configuration of SO to 80.
- the rotary switch is in forcing of SO. When a cycle is attributed to the CPU pressing "START", the AM00-07 keys are forced in SO.
- at the end of a cycle attributed to the CPU, when the rotary switch is in normal position, the future status network is stored in SO. (cpu fo. 127)
Definition at line 196 of file ge.h.
| uint8_t TO50_did_CI32_or_CI33 |
Workaround for pulse TO50.
Currently we first run the common machine logic, then the MSL states. However in certain cases (e.g. display state 00) the common TO50 implementation is conditioned on the activation of the MSL TO50... So, until we figure out a better way of factoring the MSL, let's store here the conditions for the common machine TO50, and delay its excecution to a fake TO50-1 clock pulse.
Definition at line 560 of file ge.h.
