The entire state of the emulated system, including registers, memory, peripherals and timings.
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| enum clock | current_clock |
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| uint8_t | powered |
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| struct ge_options | options |
| | Backplane straps and maintenance-panel options (cp06 ch.002).
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| struct pulse_event * | on_pulse [END_OF_STATUS] |
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| uint16_t | rPO |
| | Program addresser.
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| uint16_t | instr_pc |
| | Instruction-start PC (display aid, not a real register).
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| uint16_t | rV1 |
| | Addresser for the first operand.
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| uint16_t | rV2 |
| | Addresser for the second operand.
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| uint16_t | rV3 |
| | Addresser for external instructions using channel 3.
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| uint16_t | rV4 |
| | Addresser for external instructions using channel 2.
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| uint16_t | cr_cache [8] |
| | Change/segment-register cache (kept in sync by the register instructions via cr_wr16 and by ge_seed_segment_bases).
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| uint8_t | rRI |
| | Photoprint register 8-bit register used to store the photodisc codes.
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| uint16_t | rL1 |
| | Length of the operand.
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| uint8_t | rL2 |
| | Auxiliary register.
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| uint16_t | rL3 |
| | Length of operands involving channel 3.
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| struct ge_knot_no | kNO |
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| struct ge_knot_ni | kNI |
| | Knot driven by counting network, or by the UA to store the result of the operation.
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| uint16_t | rRO |
| | Multipurpose 8+1 bit register.
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| uint8_t | rUA |
| | UA (arithmetic unit) output latch.
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| uint16_t | rVO |
| | Default memory addresser.
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| uint16_t | rBO |
| | Default operator.
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| uint8_t | rFO |
| | Current function code.
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| uint8_t | rSO |
| | Main sequencer.
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| uint8_t | rSI |
| | Peripheral unit sequencer.
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| uint8_t | rSA |
| | Future state configuration.
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| uint8_t | rRE |
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| uint8_t | rRA |
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| uint8_t | ffFI |
| | Special conditions register 1.
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| uint8_t | ffFA |
| | Special conditions register 2.
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| uint8_t | RETO:1 |
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| uint8_t | RET2:1 |
| | Channel-2 cycle-assignment memory.
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| uint8_t | AINI:1 |
| | Program Loading.
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| uint8_t | ALOI:1 |
| | Load connector selection.
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| uint8_t | ALTO:1 |
| | Stops internal cycles.
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| uint8_t | PODI:1 |
| | Slow delay line.
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| uint8_t | ACIC:1 |
| | Recycle delay line.
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| uint8_t | ALAM:1 |
| | Operator Call.
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| uint8_t | AVER:1 |
| | Jump Condition Verified.
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| uint8_t | ADIR:1 |
| | Disable Step By Step.
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| uint8_t | ASIN:1 |
| | STEP-BY-STEP, the OPERATOR panel switch (signal ASIN).
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| uint8_t | lamps_test:1 |
| | LAMPS CHECK held (CPU[4] §3.2).
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| uint8_t | RINT:1 |
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| uint8_t | JS1:1 |
| | Console jump condition 1.
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| uint8_t | JS2:1 |
| | Console jump condition 2.
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| uint8_t | JE:1 |
| | JE/AVER jump instruction exectuted.
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| uint8_t | INTE:1 |
| | Interruption present.
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| uint8_t | PB06:1 |
| | Unconditionally stores L106.
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| uint8_t | PB07:1 |
| | Unconditionally stores L106.
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| uint8_t | PB26:1 |
| | Stores L106 if channel 2 is selected.
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| uint8_t | PB36:1 |
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| uint8_t | PB37:1 |
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| uint8_t | PIC1:1 |
| | Selection Channel 1.
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| uint8_t | RASI:1 |
| | Channel 1 in transfer.
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| uint8_t | PUC2:1 |
| | Channel 2 in transfer.
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| uint8_t | PUC3:1 |
| | Channel 3 in transfer.
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| uint8_t | PEC1:1 |
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| uint8_t | PEC1_pending:1 |
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| uint8_t | RUF1:1 |
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| uint8_t | URPE:1 |
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| uint8_t | URPU:1 |
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| uint8_t | RC00:1 |
| | Asynchronous CPU Cycle Request.
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| uint8_t | RC01:1 |
| | Asynchronous Channel 1 Cycle Request.
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| uint8_t | RC02:1 |
| | Asynchronous Channel 2 Cycle Request.
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| uint8_t | RC03:1 |
| | Asynchronous Channel 3 Cycle Request.
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| uint8_t | RIA0:1 |
| | Synchronous CPU Cycle Request.
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| uint8_t | RESI:1 |
| | Synchronous Channel 1 Cycle Request.
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| uint8_t | RIA2:1 |
| | Synchronous Channel 2 Cycle Request.
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| uint8_t | RIA3:1 |
| | Synchronous Channel 3 Cycle Request.
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| uint8_t | RECE:1 |
| | Selection Check Byte.
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| uint8_t | RIG1:1 |
| | End from controller 1.
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| uint8_t | RIG3:1 |
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| uint8_t | RACI:1 |
| | Rejected Command.
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| uint8_t | RAVI:1 |
| | VICU Support.
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| uint8_t | RT121:1 |
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| uint8_t | RT131:1 |
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| uint8_t | future_state |
| | Future state.
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| enum ge_console_rotary | register_selector |
| | The current state of the console register rotary switch.
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| struct ge_console_switches | console_switches |
| | The current state of the console switches.
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| uint8_t | step_by_step:1 |
| | Step by step execution.
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| enum ge:: { ... } | memory_command |
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| uint8_t | mem [MEM_SIZE] |
| | The memory of the emulated system.
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| uint8_t | mem_parity [MEM_SIZE] |
| | Stored odd-parity bit (1 bit per location) written alongside mem[].
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| uint8_t | mem_written [MEM_SIZE] |
| | 1 once a location has been written; prevents false MEM CHECK on cleared memory
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| uint8_t | mem_check_blank |
| | Read never-written core as a parity error (default 0).
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| uint32_t | mem_size |
| | Installed memory size; 0 is treated as MEM_SIZE (full address space)
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| uint8_t | mem_check |
| | Parity fault flag: set when a READ finds a parity mismatch on a previously-written location.
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| uint8_t | inv_add |
| | Invalid-address fault flag: set when rVO >= installed memory size.
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| uint8_t | inject_chan1_status |
| | Channel-1 peripheral status override for error injection.
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| struct ge_counting_network | counting_network |
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| struct ge_ua_controls | ua_controls |
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| struct ge_integrated_reader | integrated_reader |
| | The I/O interface for the integrated reader (RI)
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| struct ge::ge_integrated_printer | integrated_printer |
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| struct ge_connector | ST3 |
| | The I/O interface for the ST3 connector.
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| struct ge_connector | ST4 |
| | The I/O interface for the ST4 connector.
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| struct ge_channel | channel2 |
| | Integrated channel 2 (CAN2) line bundle — shared by the integrated reader (input), the printer/typewriter (output), and the keyboard.
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| struct ge_peri * | peri |
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| void * | std_core |
| | Shared core for Standard-GE-100 controllers on connectors 3/4 (disk/tape).
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| uint8_t | TO50_did_CI32_or_CI33:1 |
| | Workaround for pulse TO50.
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The entire state of the emulated system, including registers, memory, peripherals and timings.
Definition at line 172 of file ge.h.
Recycle delay line.
Initially is set by "CLEAR", after that it is reset cyclicly. The reset pulse is TO10, the normal setting pulse is TO90 if a LOLL instruction has not been performed, in this case it is set by TI05, with a delay of about 130ns. (cpu fo. 96).
NOTE: documentation differs at cpu fo. 99 that states:
The ACIC1 FF is reset by the TO10 pulse and it is set by the TO901 with the condition PODIB == 1.
PODI is the FF which stores the LOLL diagnostic instruction performance causing an increase of the cycle of about 130 ns.
In fact, if PODIB == 0 the recycling occurs with the pulse TI05 instead of TO90.
Definition at line 421 of file ge.h.
STEP-BY-STEP, the OPERATOR panel switch (signal ASIN).
A different circuit from the maintenance panel's PAPA, and independent of it (CPU[4] fo.115, the ALTO set conditions):
ASIN stops at each INSTRUCTION, through CI891 at E2/E3 of the alpha phase – the same command HLT uses – so the stop lands after the function code is read with the addresser still on the OP code (CPU[4] §5.1 b). It is subject to the program: INS inhibits it, ENS and CLEAR re-enable it, and the maintenance STOC switch overrides the inhibit. Gate: ASIN . (ATOC + !ADIR). PAPA stops after each MICROSEQUENCE, through ALS71 at the end of a CPU work cycle, "without interfering with the transfers from
peripheral unit" (CPU[4] §2.4). Not gated by the program at all.
Only this one has a lamp: STEP BY STEP on the operator panel follows ASIN, never PAPA.
Definition at line 477 of file ge.h.
LAMPS CHECK held (CPU[4] §3.2).
The momentary key sharing the MAINT ON button on the operator panel. It is a bulb test and nothing more: while it is held every console lamp lights, whatever the machine is doing, and nothing in the CPU is disturbed. Not to be pressed during a run.
Modelled here rather than in a front-end so that every console – the ncurses panel, the browser panel, anything later – gets the same test from the same place.
Definition at line 491 of file ge.h.
Read never-written core as a parity error (default 0).
Core retains, so on a machine that has been in service every cell holds something with a valid check bit and reads clean — which is what the default models, and what lets a deck read scratch it has not written yet. A machine powered up with core that has never been written is in the other state: there is no valid check bit anywhere, and running it through blank core stands MEM CHECK on. That is what the restored machine shows with nothing loaded (2026-07-31, alongside the INV ADD blink), and setting this reproduces it.
It is a property of the machine in front of you, not a rule: with it set, funktionalcpu.cap stops at cycle 57660 on a MEM CHECK at 0x00E8, a scratch cell the deck reads before writing — which on the iron holds the last program's leftovers, with their check bit.
Definition at line 720 of file ge.h.
Selection Channel 1.
Used during the general B phase for command forwarding or condition examination. Unconditionally set by command CE02 which enables the channel selection even if the interested channels are 2 or 3. When a character transfer in output has been initiated with channel 1, signal PAP4A resets PUC1 at the start of the transfer phase, when the first transfer is done from RO into RA (CE00), unless signal PAR21 had already performed that reset earlier in the status-B0 path. The CPU text explicitly says PAR21 is generated by command CI391. (cpu fo. 235, 237).
Note: the above GE docs refers to PUC2, however in intermediate block diagram fo. 10, it's shown the real flipflop is PIC1, and PUC2 is derived combinatorially from it.
Definition at line 526 of file ge.h.
Asynchronous Channel 2 Cycle Request.
It is set with the trigger LU08 from the integrated reader, or when the SITE key is inserted (RAITI1=1) during the transfers on channel 2.
Request from printer do not act on RC02, but are derived from it with an OR (RIMZA).
It is reset during a cycle of channel 2 with CE18 (enable RIAP), or at the end of a transfer on channel 2 (cpu fo. 114).
Definition at line 602 of file ge.h.
Asynchronous Channel 3 Cycle Request.
It is set with the OR of the cycle request triggers relative to channel 3 (RA301=1) if the executing instruction is not over (RIVAF=1) and additional performances of the GE-130 are enabled (FUL4F=1).
It is reset during a cycle of channel 3 with CE18 (enable RIAP), also, it is reset when the SITE key is inserted (RAITI=1) during a data transfer on channel 3 (RES36=1), or at the end of transfer on channel 3 (PIC32=0) (cpu fo. 114).
Definition at line 617 of file ge.h.
Channel-2 cycle-assignment memory.
T010-clocked latch of RES2 (cp06 ch.132-6/7/8, "OPERATING SIMULTANEITY
LOGIC": RET21 = /((RES2A·T0107)+(T010C·RET2A)), RET2A = /RET21, RET26 = /RET2A). Remembers that the current cycle was assigned to channel 2 — including the priority masking in RES2 (!RIA3 && !RESI && RIA2), which a raw RIA2 read would miss. Twin of RETO.
Definition at line 369 of file ge.h.
| uint8_t TO50_did_CI32_or_CI33 |
Workaround for pulse TO50.
Currently we first run the common machine logic, then the MSL states. However in certain cases (e.g. display state 00) the common TO50 implementation is conditioned on the activation of the MSL TO50... So, until we figure out a better way of factoring the MSL, let's store here the conditions for the common machine TO50, and delay its excecution to a fake TO50-1 clock pulse.
Definition at line 816 of file ge.h.
