The entire state of the emulated system, including registers, memory, peripherals and timings.
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| enum clock | current_clock |
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| uint8_t | halted |
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| uint8_t | powered |
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| struct pulse_event * | on_pulse [END_OF_STATUS] |
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| uint16_t | rPO |
| | Program addresser.
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| uint16_t | instr_pc |
| | Instruction-start PC (display aid, not a real register).
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| uint16_t | rV1 |
| | Addresser for the first operand.
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| uint16_t | rV2 |
| | Addresser for the second operand.
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| uint16_t | rV3 |
| | Addresser for external instructions using channel 3.
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| uint16_t | rV4 |
| | Addresser for external instructions using channel 2.
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| uint16_t | cr_cache [8] |
| | Change/segment-register CACHE used for modified-address resolution.
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| uint8_t | rRI |
| | Photoprint register 8-bit register used to store the photodisc codes.
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| uint16_t | rL1 |
| | Length of the operand.
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| uint8_t | rL2 |
| | Auxiliary register.
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| uint16_t | rL3 |
| | Length of operands involving channel 3.
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| struct ge_knot_no | kNO |
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| struct ge_knot_ni | kNI |
| | Knot driven by counting network, or by the UA to store the result of the operation.
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| uint16_t | rRO |
| | Multipurpose 8+1 bit register.
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| uint16_t | rVO |
| | Default memory addresser.
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| uint16_t | rBO |
| | Default operator.
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| uint8_t | rFO |
| | Current function code.
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| uint8_t | rSO |
| | Main sequencer.
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| uint8_t | rSI |
| | Peripheral unit sequencer.
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| uint8_t | rSA |
| | Future state configuration.
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| uint8_t | rRE |
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| uint8_t | rRA |
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| uint8_t | ffFI |
| | Special conditions register 1.
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| uint8_t | ffFA |
| | Special conditions register 2.
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| uint8_t | RETO:1 |
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| uint8_t | RET2:1 |
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| uint8_t | AINI:1 |
| | Program Loading.
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| uint8_t | ALOI:1 |
| | Load connector selection.
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| uint8_t | ALTO:1 |
| | Stops internal cycles.
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| uint8_t | PODI:1 |
| | Slow delay line.
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| uint8_t | ACIC:1 |
| | Recycle delay line.
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| uint8_t | ALAM:1 |
| | Operator Call.
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| uint8_t | AVER:1 |
| | Jump Condition Verified.
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| uint8_t | SA00:1 |
| | First-vs-second operand flag for address modification.
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| uint8_t | ADIR:1 |
| | Disable Step By Step.
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| uint8_t | RINT:1 |
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| uint8_t | JS1:1 |
| | Console jump condition 1.
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| uint8_t | JS2:1 |
| | Console jump condition 2.
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| uint8_t | JE:1 |
| | JE/AVER jump instruction exectuted.
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| uint8_t | INTE:1 |
| | Interruption present.
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| uint8_t | PB06:1 |
| | Unconditionally stores L106.
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| uint8_t | PB07:1 |
| | Unconditionally stores L106.
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| uint8_t | PB26:1 |
| | Stores L106 if channel 2 is selected.
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| uint8_t | PB36:1 |
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| uint8_t | PB37:1 |
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| uint8_t | PIC1:1 |
| | Selection Channel 1.
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| uint8_t | RASI:1 |
| | Channel 1 in transfer.
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| uint8_t | PUC2:1 |
| | Channel 2 in transfer.
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| uint8_t | PUC3:1 |
| | Channel 3 in transfer.
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| uint8_t | PEC1:1 |
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| uint8_t | PEC1_pending:1 |
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| uint8_t | RUF1:1 |
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| uint8_t | URPE:1 |
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| uint8_t | URPU:1 |
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| uint8_t | RC00:1 |
| | Asynchronous CPU Cycle Request.
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| uint8_t | RC01:1 |
| | Asynchronous Channel 1 Cycle Request.
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| uint8_t | RC02:1 |
| | Asynchronous Channel 2 Cycle Request.
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| uint8_t | RC03:1 |
| | Asynchronous Channel 3 Cycle Request.
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| uint8_t | RIA0:1 |
| | Synchronous CPU Cycle Request.
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| uint8_t | RESI:1 |
| | Synchronous Channel 1 Cycle Request.
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| uint8_t | RIA2:1 |
| | Synchronous Channel 2 Cycle Request.
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| uint8_t | RIA3:1 |
| | Synchronous Channel 3 Cycle Request.
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| uint8_t | RECE:1 |
| | Selection Check Byte.
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| uint8_t | RIG1:1 |
| | End from controller 1.
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| uint8_t | RIG3:1 |
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| uint8_t | RACI:1 |
| | Rejected Command.
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| uint8_t | RAVI:1 |
| | VICU Support.
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| uint8_t | RT121:1 |
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| uint8_t | RT131:1 |
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| uint8_t | future_state |
| | Future state.
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| enum ge_console_rotary | register_selector |
| | The current state of the console register rotary switch.
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| struct ge_console_switches | console_switches |
| | The current state of the console switches.
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| uint8_t | step_by_step:1 |
| | Step by step execution.
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| enum ge:: { ... } | memory_command |
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| uint8_t | mem [MEM_SIZE] |
| | The memory of the emulated system.
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| uint8_t | mem_parity [MEM_SIZE] |
| | Stored odd-parity bit (1 bit per location) written alongside mem[].
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| uint8_t | mem_written [MEM_SIZE] |
| | 1 once a location has been written; prevents false MEM CHECK on cleared memory
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| uint32_t | mem_size |
| | Installed memory size; 0 is treated as MEM_SIZE (full address space)
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| uint8_t | mem_check |
| | Parity fault flag: set when a READ finds a parity mismatch on a previously-written location.
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| uint8_t | inv_add |
| | Invalid-address fault flag: set when rVO >= installed memory size.
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| uint8_t | inject_chan1_status |
| | Channel-1 peripheral status override for error injection.
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| struct ge_counting_network | counting_network |
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| struct ge_integrated_reader | integrated_reader |
| | The I/O interface for the integrated reader (RI)
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| struct ge::ge_integrated_printer | integrated_printer |
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| struct ge_connector | ST3 |
| | The I/O interface for the ST3 connector.
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| struct ge_connector | ST4 |
| | The I/O interface for the ST4 connector.
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| struct ge_channel | channel2 |
| | Integrated channel 2 (CAN2) line bundle — shared by the integrated reader (input), the printer/typewriter (output), and the keyboard.
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| struct ge_peri * | peri |
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| void * | std_core |
| | Shared core for Standard-GE-100 controllers on connectors 3/4 (disk/tape).
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| uint8_t | TO50_did_CI32_or_CI33:1 |
| | Workaround for pulse TO50.
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The entire state of the emulated system, including registers, memory, peripherals and timings.
Definition at line 96 of file ge.h.
Recycle delay line.
Initially is set by "CLEAR", after that it is reset cyclicly. The reset pulse is TO10, the normal setting pulse is TO90 if a LOLL instruction has not been performed, in this case it is set by TI05, with a delay of about 130ns. (cpu fo. 96).
NOTE: documentation differs at cpu fo. 99 that states:
The ACIC1 FF is reset by the TO10 pulse and it is set by the TO901 with the condition PODIB == 1.
PODI is the FF which stores the LOLL diagnostic instruction performance causing an increase of the cycle of about 130 ns.
In fact, if PODIB == 0 the recycling occurs with the pulse TI05 instead of TO90.
Definition at line 322 of file ge.h.
Change/segment-register CACHE used for modified-address resolution.
The eight change registers are hardware-cached: addressing (EXEC_INDEX -> cr_base) reads this cache, which is updated only by the register instructions (LR/LA/AMR/SMR/JRT, via cr_wr16) and by ge_seed_segment_bases — NOT by general memory writes. This mirrors real hardware: a destructive memory test that writes the change-register shadow RAM at mem[240+2N] (0xF0-0xFF) as part of testing the 0-8K region does NOT corrupt live addressing (the CPU keeps using the cached registers), so the test's own save/restore logic can run. mem[240+2N] remains the shadow RAM the register instructions read/write and that the test exercises.
Definition at line 140 of file ge.h.
Selection Channel 1.
Used during the general B phase for command forwarding or condition examination. Unconditionally set by command CE02 which enables the channel selection even if the interested channels are 2 or 3. When a character transfer in output has been initiated with channel 1, signal PAP4A resets PUC1 at the start of the transfer phase, when the first transfer is done from RO into RA (CE00), unless signal PAR21 had already performed that reset earlier in the status-B0 path. The CPU text explicitly says PAR21 is generated by command CI391. (cpu fo. 235, 237).
Note: the above GE docs refers to PUC2, however in intermediate block diagram fo. 10, it's shown the real flipflop is PIC1, and PUC2 is derived combinatorially from it.
Definition at line 397 of file ge.h.
Asynchronous Channel 1 Cycle Request.
It is set with the OR of the channel 1 request triggers (RAI01) if the executing instruction is not over (RIVEF=1). Also, when the SITE key is inserted during a during a transfer of channel 1 (RAISI2=1). It is reset during a cycle of channel 1 with CE18 (enable RIAP), or at the end of a transfer on channel 1 (cpu fo. 114)
Definition at line 458 of file ge.h.
Asynchronous Channel 2 Cycle Request.
It is set with the trigger LU08 from the integrated reader, or when the SITE key is inserted (RAITI1=1) during the transfers on channel 2.
Request from printer do not act on RC02, but are derived from it with an OR (RIMZA).
It is reset during a cycle of channel 2 with CE18 (enable RIAP), or at the end of a transfer on channel 2 (cpu fo. 114).
Definition at line 473 of file ge.h.
Asynchronous Channel 3 Cycle Request.
It is set with the OR of the cycle request triggers relative to channel 3 (RA301=1) if the executing instruction is not over (RIVAF=1) and additional performances of the GE-130 are enabled (FUL4F=1).
It is reset during a cycle of channel 3 with CE18 (enable RIAP), also, it is reset when the SITE key is inserted (RAITI=1) during a data transfer on channel 3 (RES36=1), or at the end of transfer on channel 3 (PIC32=0) (cpu fo. 114).
Definition at line 488 of file ge.h.
Synchronous CPU Cycle Request.
Is conditioned by the signals ALTOF and RAM02.
When the FF ALTOF is reset, the cycle requests from the CPU are not serverd, therefore the internal calculation is stopped. This counter consists of the FF RAMO and RAMI and counts with the pulse TO10.
Definition at line 500 of file ge.h.
Peripheral unit sequencer.
4-bit sequencer used for data xechange with peripheral units through channel 2.
Drives the NA knot when the cycle has been attributed to channel 2.
Loaded with the first 4 bits of the future status network
- after the execution of a channel 2 cycle
- when forcing a status in SI using CU20 (DC status of general beta phase)
Definition at line 234 of file ge.h.
Main sequencer.
Drives the NA knot when the cycle has been attributed to the CPU or channel 1.
It is used to establish the sequence for:
- alpha phase for all internal and external instructions
- beta phase of internal instructions
- organisation phase (general beta) of external instructions
- program loading
Loaded from the future status network when signal SOC01 is activated, provided the RICI key is not active, in the following cases:
- the FF ARES has been set thru "CLEAR". This causes the machine to execute the status 00, and setting of SO07 using CU07, this will set the configuration of SO to 80.
- the rotary switch is in forcing of SO. When a cycle is attributed to the CPU pressing "START", the AM00-07 keys are forced in SO.
- at the end of a cycle attributed to the CPU, when the rotary switch is in normal position, the future status network is stored in SO. (cpu fo. 127)
Definition at line 220 of file ge.h.
First-vs-second operand flag for address modification.
Sequencer flag (the flow chart's <SA00> diamond, dwg 14023130) that distinguishes the FIRST operand (write the resolved effective address back to V1) from the SECOND operand (V2 only) during the modified-address indexing micro-cycle (states ED|EC -> EF|EE). Set when entering the index pass for operand 1, cleared for operand 2.
Definition at line 354 of file ge.h.
| uint8_t TO50_did_CI32_or_CI33 |
Workaround for pulse TO50.
Currently we first run the common machine logic, then the MSL states. However in certain cases (e.g. display state 00) the common TO50 implementation is conditioned on the activation of the MSL TO50... So, until we figure out a better way of factoring the MSL, let's store here the conditions for the common machine TO50, and delay its excecution to a fake TO50-1 clock pulse.
Definition at line 667 of file ge.h.
