ge.h

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#ifndef GE_H
#define GE_H
 
#include <stdint.h>
#include <stddef.h>
#include "opcodes.h"
#include "console.h"
#include "reader.h"
#include "channel.h"
 
#define CLOCK_PERIOD 14000 /* in usec, interval between pulse lines */
#define MEM_SIZE 65536
 
#define ENUMERATE_CLOCKS \
    X(TO00) \
    X(TO10) \
    X(TO11) \
    X(TO15) \
    X(TO19) \
    X(TO20) \
    X(TO25) \
    X(TO30) \
    X(TO40) \
    X(TO50) \
    X(TO50_1) \
    X(TO60) \
    X(TO64) \
    X(TO65) \
    X(TO70) \
    X(TO80) \
    X(TO89) \
    X(TO90) \
    X(TI05) \
    X(TI06) \
    X(TI10) \
    X(END_OF_STATUS)
 
enum clock {
    #define X(name) name ,
    ENUMERATE_CLOCKS
    #undef X
};
 
struct ge_counting_network {
    struct cmds {
        uint8_t from_zero:1;
        uint8_t decresing:1;
        uint8_t from_04:1;   /* count injected at bit 04 (CI42) */
        uint8_t stop_07:1;   /* carry/borrow blocked past bit 07 (CI44) */
    } cmds;
 
    /* Second-phase (CI-side) counting selection: CI40/41/42/44 stage their
     * configuration here; it becomes active when TO65 "enables the second
     * phase commands for count selection" (cpu fo. 142) — i.e. the CO-phase
     * flags are replaced by these for the TI05 loads (CI05 NI->L1 etc.).
     * This is what makes the b9/b1 per-character L1 decrement effective. */
    struct cmds ci_cmds;
};
 
/* Arithmetic-unit mode lines selected by CI45/CI46/CI47 for the duration of
 * one sequencer state.  Their combinations are decoded by CI68/CI69 when the
 * UA result is admitted to the NI knot. */
struct ge_ua_controls {
    uint8_t logic:1;          /* CI45: logical-operation group */
    uint8_t decimal_and:1;    /* CI46: decimal / AND group */
    uint8_t subtract_xor:1;   /* CI47: subtract / XOR group */
 
    /* CI50, "OPERA SOLO UA1 / WORK ONLY UA1" (cp07 fo.142).  Not a function
     * select: cp06 ch.094 shows CI50B = /CI501 feeding the UZE71 and UZE81
     * NANDs, so asserting CI50 INHIBITS the inter-zone enables and leaves
     * only the low unit participating.  It gates the arithmetic unit's
     * WIDTH, which is what a digit-at-a-time decimal operation needs. */
    uint8_t low_zone_only:1;  /* CI50: inhibit UZE71/UZE81 */
};
 
struct ge_knot_no {
    uint8_t forcings;
 
    enum {
        KNOT_FORCING_NONE,
        KNOT_FORCING_NO_21,
        KNOT_FORCING_NO_43,
    } force_mode;
 
    enum {
        KNOT_PO_IN_NO,
        KNOT_V1_IN_NO,
        KNOT_V2_IN_NO,
        KNOT_V3_IN_NO,
        KNOT_V4_IN_NO,
        KNOT_L1_IN_NO,
        KNOT_L2_IN_NO,
        KNOT_L3_IN_NO,
        KNOT_AM_IN_NO,
        KNOT_RI_IN_NO_43,
        /* Explicit "no selection drives the knot": hardware selections are
         * pulses, so a knot with no active selection reads 0 at latch time.
         * gemu's cmd persists across pulses; NO_UNDRIVEN models the decay
         * where a sheet's data path depends on it (interruption D3). */
        KNOT_NONE_IN_NO,
    } cmd;
};
 
enum knot_ni_source {
    NS_ZERO,   /* quartet driven by nothing: non-storing knot reads 0 */
    NS_CN1,
    NS_CN2,
    NS_CN3,
    NS_CN4,
    NS_RO1,
    NS_RO2,
    NS_UA2,
    NS_UA1,
};
 
struct ge_knot_ni {
    enum knot_ni_source ni1;
    enum knot_ni_source ni2;
    enum knot_ni_source ni3;
    enum knot_ni_source ni4;
};
 
/* Strap-card types actually printed in the ch.001/ch.002 tables: only PONT2N
 * and PONT2P exist.  "PONT2H" was a misread of PONT2N in the 1968 typeface,
 * caught when the physical machine's cards were identified (2026-07-21):
 * 0618034Z reads PONT2N on the board, and 0618035V is electrically a PONT2N
 * too, under a different part code. */
enum ge_pont { PONT_NONE = 0, PONT_2N, PONT_2P };
 
struct ge_options {
    enum ge_pont E03;
 
    enum ge_pont E04;
 
    enum ge_pont F03;
 
    enum ge_pont F04;
 
    enum ge_pont E05;
    enum ge_pont F05;
 
    uint8_t S42_diag;
};
 
struct ge {
    /* Main clock */
    enum clock current_clock;
    uint8_t powered;
 
    struct ge_options options;
 
    /* Lists of events and operations for all
     * pulses
     */
    struct pulse_event *on_pulse[END_OF_STATUS];
 
    uint16_t rPO;
 
    uint16_t instr_pc;
 
    uint16_t rV1; 
    uint16_t rV2; 
    uint16_t rV3; 
    uint16_t rV4; 
 
    uint16_t cr_cache[8];
 
    uint8_t rRI;
 
    uint16_t rL1;
    uint8_t  rL2; 
    uint16_t rL3; 
 
    struct ge_knot_no kNO;
 
    struct ge_knot_ni kNI;
 
    uint16_t rRO;
 
    uint8_t rUA;
 
    uint16_t rVO;
 
    uint16_t rBO;
 
    uint8_t rFO;
 
    uint8_t rSO;
 
    uint8_t rSI;
 
    uint8_t rSA;
 
    uint8_t rRE;
    uint8_t rRA;
 
    uint8_t ffFI;
 
    uint8_t ffFA;
 
    /* Those two store which work channel the present cycle as been attributed to
     * (cpu fo. 130).
     * When setting RETO, if PAPA switch is set, rotary is neither in normal, nor
     * in position 8 to store in memory, should set ALTO */
    uint8_t RETO:1;
 
    uint8_t RET2:1;
 
    uint8_t AINI:1;
 
    uint8_t ALOI:1;
 
    uint8_t ALTO:1;
 
    uint8_t PODI:1;
 
    uint8_t ACIC:1;
 
    uint8_t ALAM:1;
 
    uint8_t AVER:1;
 
    /* The flow chart's <SA00> first-vs-second operand diamond (dwg 14023130)
     * is bit 0 of the SA state code itself: E6 routes operand 1 to ED (bit 0
     * set, via its unconditional CU00) and E7 routes operand 2 to EC (bit 0
     * cleared by CU10 = DI64A0) — see the indexing states in msl-states.c.
     * No separate flag is needed. */
 
    uint8_t ADIR:1;
 
    uint8_t ASIN:1;
 
    uint8_t lamps_test:1;
 
    uint8_t RINT:1;
 
    uint8_t JS1:1;  
    uint8_t JS2:1;  
    uint8_t JE:1;   
    uint8_t INTE:1; 
 
    /* Busy Connector Logic */
 
    uint8_t PB06:1; 
    uint8_t PB07:1; 
    uint8_t PB26:1; 
    uint8_t PB36:1;
    uint8_t PB37:1;
 
    uint8_t PIC1:1;
 
    uint8_t RASI:1;
 
    uint8_t PUC2:1;
 
    uint8_t PUC3:1;
 
    uint8_t PEC1:1;
    uint8_t PEC1_pending:1;
 
    uint8_t RUF1:1;
 
    uint8_t URPE:1;
    uint8_t URPU:1;
 
    /* Cycle Attribution Logic */
    /* ----------------------- */
 
    /* Asyncronous flip flops */
 
    uint8_t RC00:1;
 
    uint8_t RC01:1;
 
    uint8_t RC02:1;
 
    uint8_t RC03:1;
 
    uint8_t RIA0:1;
 
    uint8_t RESI:1;
 
    uint8_t RIA2:1;
 
    uint8_t RIA3:1;
 
    uint8_t RECE:1;
 
    uint8_t RIG1:1;
 
    uint8_t RIG3:1;
 
    uint8_t RACI:1;
 
    uint8_t RAVI:1;
 
    uint8_t RT121:1;
    uint8_t RT131:1;
 
    uint8_t future_state;
 
    enum ge_console_rotary register_selector;
 
    struct ge_console_switches console_switches;
 
    uint8_t step_by_step:1;  
 
    enum {
        MC_NONE,
        MC_READ,
        MC_WRITE,
    } memory_command;
 
    uint8_t mem[MEM_SIZE]; 
 
    uint8_t mem_parity[MEM_SIZE];
 
    uint8_t mem_written[MEM_SIZE];
 
    uint8_t mem_check_blank;
 
    uint32_t mem_size;
 
    uint8_t mem_check;
 
    uint8_t inv_add;
 
    uint8_t inject_chan1_status;
 
    struct ge_counting_network counting_network;
    struct ge_ua_controls ua_controls;
 
    struct ge_integrated_reader integrated_reader;
 
    struct ge_integrated_printer {
        int      present;
        char     out[65536];    /* captured printed chars; per-frame staging only
                                 * (the wasm console drains+clears each frame, the
                                 * CLI reads it at end). Sized for a catch-up
                                 * frame's burst so fast/backgrounded printing
                                 * doesn't overflow before the drain. */
        int      out_len;
        uint8_t  kbd[256];      /* operator keyboard input queue */
        int      kbd_head, kbd_tail;
        /* Channel-2 OUTPUT transfer engine (printer.c): while out_active, the
         * printer requests a channel-2 cycle (RC02) per character so the rSI
         * output state (0x02) drains out_remaining bytes from V4, then ends.
         * out_saved_so preserves the CPU sequencer across the (overlapped)
         * transfer — fsn advances SO on RIA0, which the stolen channel-2 cycles
         * would otherwise clobber; we restore it when the transfer ends. */
        int      out_active;
        int      out_remaining;
        int      out_total;
        int      out_line_mode;
        uint8_t  out_saved_so;
    } integrated_printer;
 
    struct ge_connector ST3;
 
    struct ge_connector ST4;
 
    struct ge_channel channel2;
 
    struct ge_peri *peri;
 
    void *std_core;
 
    uint8_t TO50_did_CI32_or_CI33:1;
};
 
void ge_init(struct ge *ge);
 
int ge_deinit(struct ge *ge);
 
int ge_load_image(struct ge *ge, const uint8_t *image, size_t size,
                  uint16_t origin);
 
void ge_enter(struct ge *ge, uint16_t entry);
 
void ge_mem_store8(struct ge *ge, uint16_t addr, uint8_t val);
 
void ge_seed_segment_bases(struct ge *ge);
 
int ge_run(struct ge *ge);
 
int ge_run_pulse(struct ge *ge);
 
int ge_run_cycle(struct ge *ge);
 
void ge_clear(struct ge * ge);
 
void ge_load(struct ge * ge);
 
void ge_load_1(struct ge * ge);
 
void ge_load_2(struct ge * ge);
 
void ge_start(struct ge * ge);
 
typedef void (*on_pulse_cb)(struct ge *);
 
struct pulse_event {
    on_pulse_cb cb;
    struct pulse_event *next;
};
 
/* Defined in pulse.c: execute pulse events */
void pulse(struct ge *ge);
 
struct ge_peri {
    struct ge_peri *next;
    int (*init)(struct ge*, void*);
    int (*on_pulse)(struct ge*, void*);
    int (*on_clock)(struct ge*, void*);
    int (*deinit)(struct ge*, void*);
    void *ctx;
};
 
int ge_register_peri(struct ge *ge, struct ge_peri *p);
 
void fsn_last_clock(struct ge *ge);
 
void connectors_first_clock(struct ge *ge);
 
const char *ge_clock_name(enum clock c);
 
void ge_print_registers_verbose(struct ge *ge);
 
static inline uint8_t ge_halted(const struct ge *ge) { return ge->ALTO; }
 
void ge_log_options(struct ge *ge);
 
#endif /* GE_H */