signals.h

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#ifndef SIGNALS_H
#define SIGNALS_H
 
#include <stdint.h>
#include "bit.h"
#include "ge.h"
#include "log.h"
 
#define SIG( name ) static inline uint8_t name (struct ge *ge)
 
SIG(RESI)  { return  ge->RESI;  }
SIG(RESI1) { return  RESI(ge);  }
SIG(RESIA) { return !RESI1(ge); }
SIG(RIA01) { return  ge->RIA0;  }
SIG(RIA2A) { return !ge->RIA2;  }
SIG(RIA3A) { return !ge->RIA3;  }
 
SIG(RIUCA) { return !(RIA01(ge) && RESIA(ge) && RIA2A(ge) && RIA3A(ge)); }
 
/* adding RIUCA here breaks machine startup */
SIG(RES01) { return !(RESIA(ge) /* && RIUCA(ge) */); }
 
SIG(RES0)  { return RES01(ge); }
 
SIG(RES2) {
    /* cpu fo. 116 */
    /* maybe this equation is incorrect in manual? it's
     * documented as `!RIA2`, but it seems it should not
     * be negated. */
    return !ge->RIA3 & !ge->RESI & ge->RIA2;
}
 
SIG(RES3) {
    /* cpu fo. 115 */
    return ge->RIA3 & !ge->RESI;
}
 
SIG(RIUC) {
    return ge->RIA0 & !ge->RESI & !ge->RIA3 & !ge->RIA2;
}
 
SIG(RES31) { return RES3(ge); };
 
SIG(verified_condition) {
    /* cpu fo 56, 57 */
    uint8_t M = ge->rL1;
    uint8_t M7 = BIT(M, 7);
    uint8_t M6 = BIT(M, 6);
    uint8_t M5 = BIT(M, 5);
    uint8_t M4 = BIT(M, 4);
 
    uint8_t FA5 = BIT(ge->ffFA, 5);
    uint8_t FA4 = BIT(ge->ffFA, 4);
 
    return (((ge->rFO == JC_OPCODE || ge->rFO == JU_OPCODE || ge->rFO == JCC_OPCODE ||
              ge->rFO == JRT_OPCODE) &&
             ((M7 && !FA4 && !FA5) ||
              (M6 && !FA4 &&  FA5) ||
              (M5 &&  FA4 && !FA5) ||
              (M4 &&  FA4 &&  FA5))) ||
            (ge->rFO == JS1_OPCODE && (ge->rL1 & 0xFF) ==JS1_2NDCHAR && ge->JS1) ||
            (ge->rFO == JS2_OPCODE && (ge->rL1 & 0xFF) ==JS2_2NDCHAR && ge->JS2) ||
            0);
}
 
SIG(AF10) { return ge->register_selector == RS_V4;      }
 
SIG(AF20) { return ge->register_selector == RS_L3;      }
 
SIG(AF21) { return ge->register_selector == RS_L1;      }
 
SIG(AF30) { return ge->register_selector == RS_V3;      }
 
SIG(AF31) { return ge->register_selector == RS_V1;      }
 
SIG(AF32) { return ge->register_selector == RS_NORM;    }
 
SIG(AF40) { return ge->register_selector == RS_R1_L2;   }
 
SIG(AF41) { return ge->register_selector == RS_V1_SCR;  }
 
SIG(AF42) { return ge->register_selector == RS_PO;      }
 
SIG(AF43) { return ge->register_selector == RS_SO;      }
 
SIG(AF50) { return ge->register_selector == RS_V2;      }
 
SIG(AF51) { return ge->register_selector == RS_V1_LETT; }
 
SIG(AF52) { return ge->register_selector == RS_FI_UR;   }
 
SIG(AF53) { return ge->register_selector == RS_FO;      }
static inline uint16_t ge_counting_network_output(struct ge *ge) {
    /* The flow charts spell an increment as CO41 (from_zero) alone and a
     * decrement as CO40+CO41 (decreasing+from_zero): V1+1->V1 is "...41...",
     * V1-1->V1 and L1-1->L1 are "...40-41...". CI42 injects the count at bit
     * 04 instead, and CI44 blocks the carry/borrow past bit 07 (byte-local
     * count). The active flags are the CO-phase ones until TO65 swaps in the
     * CI-phase staging (pulse.c). (CPU[7] p33 external charts; fo.38/62 CI
     * rows.)
     *
     * from_zero AND from_04 together are TWO INDEPENDENT QUARTET COUNTERS,
     * not one subtraction of 0x11. cp06 ch.097 gate 24 (U13) builds BUD01 --
     * the term that drives quartet 2's carry chain over on ch.096 -- from
     * CA41A, CA42B and CA431 alone, all command lines, with no carry term
     * from the bits 00-03 chain in it. So quartet 2 counts because it was
     * TOLD to, not because quartet 1 borrowed into it, and a borrow out of
     * bit 03 must not disturb it.
     *
     * That is what the decimal families need: cp07 fo.141 raises CI41 and
     * CI42 from one gate, and fo.143 reads the two quartets separately --
     * {L1_1 = 1i} switches the loop into its X variant (60 -> 62) while only
     * {L1_2 = 1i} leaves for E2/E3. L1's low byte carries one length per SS
     * operand, and the shorter one running out must not shorten the other. */
    struct cmds *c = &ge->counting_network.cmds;
    uint16_t delta = 0;
 
    if (c->from_zero && c->from_04) {
        uint8_t lo = ge->rBO & 0x0f;
        uint8_t hi = (ge->rBO >> 4) & 0x0f;
 
        if (c->decresing) {
            lo = (lo - 1) & 0x0f;
            hi = (hi - 1) & 0x0f;
        } else {
            lo = (lo + 1) & 0x0f;
            hi = (hi + 1) & 0x0f;
        }
        return (ge->rBO & 0xff00) | (uint16_t)(hi << 4) | lo;
    }
 
    if (c->from_zero)
        delta += 1;
    if (c->from_04)
        delta += 0x10;
    if (!delta)
        return ge->rBO;
    if (c->decresing) {
        if (c->stop_07)
            return (ge->rBO & 0xff00) | ((ge->rBO - delta) & 0x00ff);
        return ge->rBO - delta;
    }
    if (c->stop_07)
        return (ge->rBO & 0xff00) | ((ge->rBO + delta) & 0x00ff);
    return ge->rBO + delta;
}
 
static inline uint16_t NO_knot(struct ge *ge)
{
    uint16_t no = 0;
 
    switch (ge->kNO.cmd) {
        case KNOT_PO_IN_NO:
            no = ge->rPO;
            break;
        case KNOT_V1_IN_NO:
            no = ge->rV1;
            break;
        case KNOT_V2_IN_NO:
            no = ge->rV2;
            break;
        case KNOT_V3_IN_NO:
            no = ge->rV3;
            break;
        case KNOT_V4_IN_NO:
            no = ge->rV4;
            break;
        case KNOT_L1_IN_NO:
            no = ge->rL1;
            break;
        case KNOT_L2_IN_NO:
            no = ge->rL2;
            break;
        case KNOT_L3_IN_NO:
            no = ge->rL3;
            break;
        case KNOT_AM_IN_NO:
            no = ge->console_switches.AM;
            break;
        case KNOT_RI_IN_NO_43:
            no = ge->rRI << 8;
            break;
        case KNOT_NONE_IN_NO:
            no = 0;
            break;
    }
 
    switch (ge->kNO.force_mode) {
        case KNOT_FORCING_NONE:
            break;
        case KNOT_FORCING_NO_21:
            /* "Forcing in NO21" (CO18): the forcings drive quartets 2,1.
             * In every state that raises CO18 with an address build (the
             * indexing micro-cycle ED|EC / EF|EE, CPU[7] p64), no register
             * selection is active while BO/VO latch the knot at TO20 — the
             * selection commands are pulsed later in the cycle — so the knot
             * carries the forced byte alone (quartets 4,3 read 0). gemu's
             * kNO.cmd persists across cycles, so the previous state's
             * selection must not leak into the forced address here. */
            no = ge->kNO.forcings;
            break;
        case KNOT_FORCING_NO_43:
            /* "Forcing in NO43" (CI19): forcings drive quartets 4,3 on top
             * of whatever selection still drives them, and the low quartets
             * are blanked (the TPER-CPER a8/a9 flow depends on both). Where
             * a sheet's data path instead needs the PURE forced byte because
             * the selection pulse has decayed (interruption F0/D2), the
             * state issues NO_UNDRIVEN first — see KNOT_NONE_IN_NO. */
            no = (no & 0xff00) | (ge->kNO.forcings << 8);
            break;
    }
 
    return no;
}
 
static inline uint8_t NA_knot(struct ge *ge) {
    uint8_t na = 0;
 
    if (RES0(ge) || (RIUC(ge) && AF32(ge)))
        na = ge->rSO;
 
    if (RES2(ge))
        na = ge->rSI & 0x0f;
 
    if (RES0(ge) || RES3(ge))
        na = na | 0x01;
 
    if (RIUC(ge) && !AF32(ge))
        na = na | 0x08;
 
    return na;
}
 
static inline uint8_t NI_source(struct ge *ge, enum knot_ni_source source) {
    uint16_t cn = ge_counting_network_output(ge);
 
    switch (source) {
        case NS_ZERO:
            return 0;
        case NS_CN1:
            return (cn & 0x000f) >>  0;
        case NS_CN2:
            return (cn & 0x00f0) >>  4;
        case NS_CN3:
            return (cn & 0x0f00) >>  8;
        case NS_CN4:
            return (cn & 0xf000) >> 12;
        case NS_RO1:
            return (ge->rRO & 0x0f) >> 0;
        case NS_RO2:
            return (ge->rRO & 0xf0) >> 4;
        case NS_UA2:
            return (ge->rUA & 0xf0) >> 4;
        case NS_UA1:
            return (ge->rUA & 0x0f) >> 0;
    }
}
 
static inline uint16_t NI_knot(struct ge *ge) {
    uint16_t ni1 = NI_source(ge, ge->kNI.ni1);
    uint16_t ni2 = NI_source(ge, ge->kNI.ni2);
    uint16_t ni3 = NI_source(ge, ge->kNI.ni3);
    uint16_t ni4 = NI_source(ge, ge->kNI.ni4);
 
    return ((ni4 << 12) |
            (ni3 <<  8) |
            (ni2 <<  4) |
            (ni1 <<  0));
}
 
SIG(DI01A) { return !(BIT(ge->rSA, 0) && !BIT(ge->rSA, 1)); }
SIG(DI011) { return !DI01A(ge); }
SIG(DI02A) { return !(BIT(ge->rSA, 0) && BIT(ge->rSA, 1)); }
SIG(DI021) { return !DI02A(ge); }
SIG(DI03A) { return !(BIT(ge->rSA, 0) && BIT(ge->rSA, 1)); }
SIG(DI031) { return !DI03A(ge); }
SIG(DI06A) { return !(!BIT(ge->rSA, 7) && BIT(ge->rSA, 6) && BIT(ge->rSA, 2)); }
SIG(DI062) { return !DI06A(ge); }
/* cp06 ch.241-11: a second inverter off the same DI06A net, carrying the
 * identical value to DI062.  The two exist only to split fan-out -- the
 * function/status AND sheets draw some of their beta-band terms from one and
 * some from the other.  Kept distinct so each gate reads like its sheet. */
SIG(DI061) { return !DI06A(ge); }
SIG(DI10A) { return !(BIT(ge->rSA, 7) && BIT(ge->rSA, 6) && BIT(ge->rSA, 5) && !BIT(ge->rSA, 4)); }
SIG(DI101) { return !DI10A(ge); }
SIG(DI11A) { return !(BIT(ge->rSA, 3) && DI101(ge) && !BIT(ge->rSA, 2)); }
SIG(DI111) { return !DI11A(ge); }
SIG(DI12A) { return !(!BIT(ge->rSA, 3) && DI101(ge)); }
SIG(DI121) { return !DI12A(ge); }
SIG(DI14A) { return !(BIT(ge->rSA, 7) && !BIT(ge->rSA, 5) && BIT(ge->rSA, 6)); }
SIG(DI141) { return !DI14A(ge); }
SIG(DI15A) { return !(DI141(ge) && !BIT(ge->rSA, 3)); }
SIG(DI151) { return !DI15A(ge); }
SIG(DI17A) { return !(!BIT(ge->rSA, 1) && DI121(ge) && !BIT(ge->rSA, 2)); }
SIG(DI18A) { return !(!BIT(ge->rSA, 2) && DI121(ge) && BIT(ge->rSA, 1)); }
SIG(DI181) { return !DI18A(ge); }
SIG(DI18B) { return !DI181(ge); }
SIG(DI19A) { return !(!BIT(ge->rSA, 1) && DI121(ge) && BIT(ge->rSA, 2)); }
SIG(DI20A) { return !(BIT(ge->rSA, 1) && BIT(ge->rSA, 2) && DI121(ge)); }
/* DI201 = /DI20A (the E6|E7 state decode, active-high). Was transcribed as
 * DI201 = DI20A, which made EC56A0 (the modified-address CU03 gate in E6/E7,
 * timing tables CPU[7] p63) a constant 0 — the reason the indexing micro-cycle
 * previously needed future-state forcing instead of its documented CU rows. */
SIG(DI201) { return !DI20A(ge); }
/* State decodes for the modified-address indexing micro-cycle (timing tables
 * CPU[7] p64, "FASE ALFA ED-EC / EF-EE"). The xxA equations are derived from
 * the state codes; audit round-2 evidence from the cp06 sheets:
 *  - DI13A = NAND(DI101, SA03, SA02) READ on ch.225-18 — matches exactly.
 *  - DI65A reconstructed from fan-out callouts as NAND(DI131, SA01M)
 *    == this derivation (the generating ch.239 sheet is missing from the
 *    scan — see DI60A below).
 *  - DI67A partially reconstructed as NAND(DI031, ...): DI031 = SA00·SA01,
 *    functionally identical to this derivation (DI13·SA1·SA0 = EF).
 *  - DI66A partially reconstructed (SA016 confirmed as one input).
 *  - DI64A EXISTS at ch.232-19 (p292, read at 600dpi; missing from the
 *    parsed signal index — DI181-style parser gap); it is an inverter there,
 *    upstream AND-decode not yet located. Derived E7-only equation kept. */
SIG(DI13A) { return !(DI101(ge) && BIT(ge->rSA, 3) && BIT(ge->rSA, 2)); }  /* ED|EC + EF|EE */
SIG(DI64A) { return !(DI121(ge) && BIT(ge->rSA, 2) &&
                      BIT(ge->rSA, 1) && BIT(ge->rSA, 0)); }               /* E7 only */
SIG(DI65A) { return !(!DI13A(ge) && !BIT(ge->rSA, 1)); }                   /* ED|EC only */
SIG(DI66A) { return !(!DI13A(ge) && BIT(ge->rSA, 1)); }                    /* EF|EE only */
SIG(DI67A) { return !(!DI66A(ge) && BIT(ge->rSA, 0)); }                    /* EF|EE, 1st operand {SA00} */
SIG(DI21A) { return !( DI141(ge) && BIT(ge->rSA, 4) && BIT(ge->rSA, 3) && !BIT(ge->rSA, 2)); }
SIG(DI211) { return !DI21A(ge); }
SIG(DI22A) { return !(DI141(ge) && BIT(ge->rSA, 4) && BIT(ge->rSA, 3) && BIT(ge->rSA, 2)); }
SIG(DI23A) { return !(DI141(ge) && BIT(ge->rSA, 3) && !BIT(ge->rSA, 4)); }
SIG(DI231) { return !DI23A(ge); }
SIG(DI24A) { return !(DI231(ge) && BIT(ge->rSA, 2)); };
SIG(DI25A) { return !( DI231(ge) && !BIT(ge->rSA, 1) && !BIT(ge->rSA, 2)); };
SIG(DI27A) { return !(!BIT(ge->rSA, 4) && !BIT(ge->rSA, 6) && BIT(ge->rSA, 7)); }
SIG(DI271) { return !DI27A(ge); }
SIG(DI28A) { return !(DI271(ge) && !BIT(ge->rSA, 5)); }
SIG(DI281) { return !DI28A(ge); }
SIG(DI28B) { return !DI281(ge); }
SIG(DI29A) { return !(DI271(ge) && BIT(ge->rSA, 5) && BIT(ge->rSA, 3)); };
SIG(DI291) { return !DI29A(ge); }
SIG(DI48A) { return !(!BIT(ge->rSA, 4) && !BIT(ge->rSA, 5) && !BIT(ge->rSA, 6) && !BIT(ge->rSA, 7)); }
SIG(DI481) { return !DI48A(ge); }
SIG(DI58A) { return !(BIT(ge->rSA, 3) && !BIT(ge->rSA, 6)); }
SIG(DI581) { return !DI58A(ge); }
SIG(DI69A) { return !(DI481(ge) && !BIT(ge->rSA, 2)); }
SIG(DI691) { return !DI69A(ge); }
SIG(DI57A) { return !(!BIT(ge->rSA, 1) && DI581(ge) && DI691(ge)); }
SIG(DI572) { return !DI57A(ge); }
SIG(DI57B) { return DI57A(ge) ; }
SIG(DI79A) { return !(DI151(ge) && DI021(ge)); }
/* DI82A/DI83A live on the same missing ch.239 sheet as DI60A (see above).
 * DI82A = NAND(DI111 [274-11], SA006 [110-2]) reconstructed from fan-out
 * callouts (medium confidence): the E9|EB decode. Currently unused by any
 * state table. */
SIG(DI82A) { return !(DI111(ge) && BIT(ge->rSA, 0)); }
/* DI83A: only one input recovered from callouts (SA00F = /SA00); the second
 * input is unrecoverable without the missing sheet. Kept as the historical
 * stub (DI83A0 = 0, so state_ea's CI33 row stays inert) rather than guessing
 * an equation that could change state_ea behavior. */
SIG(DI83A) { return 1; } // ch.239 sheet missing from scan; eq. partially known
SIG(DI84A) { return !(DI011(ge) && DI291(ge)); }
SIG(DI85A) { return !(DI291(ge) && DI031(ge)); }
SIG(DI86A) { return !(!BIT(ge->rSA, 0) && DI291(ge)); }
SIG(DI87A) { return !(!BIT(ge->rSA, 1) && DI291(ge)); }
SIG(DI91A) { return !(DI031(ge) && DI211(ge)); }
SIG(DI931) { return !(DI21A(ge) && DI29A(ge) && DI21A(ge) && DI15A(ge)); }
SIG(DI93A) { return !DI931(ge); }
SIG(DI94A) { return !(BIT(ge->rSA, 0) && DI931(ge)); }
SIG(DI95A) { return !(DI931(ge) && DI031(ge)); }
SIG(DI971) { return !(DI29A(ge) && DI25A(ge) && DI24A(ge) && DI29A(ge)); }
SIG(DI97A) { return !DI971(ge); }
 
SIG(DO01A) { return !(BIT(ge->rFO, 6) && !BIT(ge->rFO, 3) && !BIT(ge->rFO, 7)); }
SIG(DO011) { return !DO01A(ge); }
SIG(DO02A) { return !(BIT(ge->rFO, 3) && !BIT(ge->rFO, 7) && BIT(ge->rFO, 6)); }
SIG(DO021) { return !(DO02A(ge) && DO02A(ge)); }
SIG(DO04A) { return !(!BIT(ge->rFO, 5) && BIT(ge->rFO, 7)); }
SIG(DO041) { return !DO04A(ge); }
/* Backplane option connectors, cp06 ch.002 "VARIANTI E OPZIONI".
 *
 * TAB.3 -- E04 selects which two connectors are enabled for the initial LOAD:
 *
 *   E04      || FUL26 | FUL36 || connectors enabled for loading
 *   ---------++-------+-------++--------------------------------
 *   (empty)  ||   1   |   1   || 2 and 3
 *   PONT2N   ||   1   |   0   || 2 and 4
 *   PONT2P   ||   0   |   1   || 4 and 3
 *
 * gemu defaults to empty, which is what the initial-load tests assume. */
SIG(FUL26) { return ge->options.E04 != PONT_2P; }
SIG(FUL36) { return ge->options.E04 != PONT_2N; }
 
/* TAB.1 selection signals for the processor version.  FEL06 is high only on
 * the 6 usec UCE 466; FEL16 separates the 4 usec 467 from the 2 usec 468. */
SIG(FEL06) { return ge->options.E03 == PONT_NONE; }
SIG(FEL16) { return ge->options.E03 != PONT_2N; }
 
/* TAB.1 + TAB.2 -- which connectors may raise an interruption.  A strapped
 * F04 is one of the "interruptions NO" versions and holds both low; only an
 * empty F04 lets F03 choose, per TAB.2: empty enables both connectors,
 * PONT2N enables 3 alone, PONT2P enables 4 alone. */
SIG(INES3) {
    return ge->options.F04 == PONT_NONE && ge->options.F03 != PONT_2P;
}
SIG(INES4) {
    return ge->options.F04 == PONT_NONE && ge->options.F03 != PONT_2N;
}
 
static inline uint16_t ge_cpu_version_uce(const struct ge *ge)
{
    if (ge->options.E03 == PONT_NONE) return 466;   /* 6 usec, MIN */
    if (ge->options.E03 == PONT_2P)   return 467;   /* 4 usec, MAX */
    return 468;                                     /* 2 usec, MAX */
}
 
static inline uint16_t ge_cycle_period_ns(const struct ge *ge)
{
    switch (ge_cpu_version_uce(ge)) {
        case 466: return 6000;
        case 467: return 4000;
        default:  return 2000;
    }
}
 
/* Memory capacity, cp06 ch.001 "SELEZIONE CAPACITA' MEMORIA / MEMORY
 * CAPABILITY SELECTION" (dwg 14013 065 6).  E05 and F05 between them pick one
 * of five sizes, and the three selection signals fall out as:
 *
 *   version  | memory | E05    | F05    || VAMA2 | VEMB6 | VAMC2
 *   ---------+--------+--------+--------++-------+-------+-------
 *   UCE 460  |   8K   | /      | /      ||   1   |   1   |   1
 *   UCE 461  |  12K   | PONT2N | /      ||   1   |   1   |   0
 *   UCE 462  |  16K   | /      | PONT2N ||   1   |   0   |   1
 *   UCE 463  |  24K   | PONT2P | PONT2N ||   0   |   0   |   1
 *   UCE 464  |  32K   | PONT2N | PONT2P ||   0   |   0   |   0
 *
 * Note the UCE numbering runs on two independent axes: 460-464 is the memory
 * capacity, 466-468 the processor version on ch.002.  A machine is one of
 * each, which is why every title block reads "UCE 460" -- that is the drawing
 * set, not the machine.
 *
 * HOW THE CARDS WORK (derived 2026-07-21, over-determined by the ch.001 +
 * ch.002 tables jointly and corroborated by the photographed boards): the
 * PONT2 is a generic strap card and the type is which pins its staples
 * short to the common --
 *
 *     PONT2N shorts pins {1, 4}        PONT2P shorts pins {1, 3}
 *
 * One assignment reproduces every printed row of TAB.1/TAB.2/TAB.3 and the
 * ch.001 capacity table simultaneously (FEL06=1/FEL16=4 on E03, INES3=3/
 * INES4=4 on F03, FUL26=3/FUL36=4 on E04, VAMC2=4/VAMA2=3 on E05,
 * VEMB6=1/VAMA2=3 on F05, and on F04 it places FUL4G on pin 4 with the
 * interrupt inhibit on pin 1 -- explaining why BOTH card types disable
 * interrupts there).  The signal equations below are written from that
 * mechanism, not fitted to the table rows: the difference shows only for
 * strap combinations the tables never print, e.g. E05=N,F05=N, where the
 * old fitted VAMA2 wrongly read 0. */
SIG(VAMC2) { return ge->options.E05 != PONT_2N; }
SIG(VEMB6) { return ge->options.F05 == PONT_NONE; }
SIG(VAMA2) {
    /* pin 3 is grounded only by a PONT2P, in either position */
    return !(ge->options.E05 == PONT_2P || ge->options.F05 == PONT_2P);
}
 
/* The S42 "LAMPS" override again, exactly as on ch.002: VAMA1/VAMB1/VAMC1
 * follow VAMA2/VEMB6/VAMC2 unless the switch is in DIAG, when they become
 * 1 / 0 / 1 regardless of the straps. */
SIG(VAMA1) { return ge->options.S42_diag ? 1 : VAMA2(ge); }
SIG(VAMB1) { return ge->options.S42_diag ? 0 : VEMB6(ge); }
SIG(VAMC1) { return ge->options.S42_diag ? 1 : VAMC2(ge); }
 
static inline uint8_t ge_mem_in_bounds(struct ge *ge, uint16_t addr)
{
    uint8_t b12 = !!(addr & 0x1000), b13 = !!(addr & 0x2000),
            b14 = !!(addr & 0x4000);
    uint8_t A = VAMA1(ge), B = VAMB1(ge), C = VAMC1(ge);
 
    if (b13 && A && B && C)  return 0;   /* VAM11: past  8K */
    if (b14 && A)            return 0;   /* VAM21: past 16K */
    if (b13 && b12 && B)     return 0;   /* VAM31: past 12K */
    if (b14 && b13 && C)     return 0;   /* VAM41: past 24K */
    return 1;
}
 
static inline uint16_t ge_memory_capacity_k(struct ge *ge)
{
    /* The effective bound the ch.080 gates enforce: the first 4K frame
     * whose start address the memory refuses to cycle for.  For the five
     * printed ch.001 rows this lands on the table's own 8/12/16/24/32K;
     * for off-table strap combinations (e.g. the N+N found at Electric
     * Dreams, which reads (1,0,0) -> 16K) it is the machine's real,
     * gate-derived behaviour rather than a guess. */
    for (uint32_t a = 0x1000; a < 0x8000; a += 0x1000)
        if (!ge_mem_in_bounds(ge, (uint16_t)a))
            return (uint16_t)(a >> 10);
    return 32;
}
 
/* TAB.1 -- E03 and F04 strap the machine version, and FUL4G distinguishes the
 * slow minimum-performance model from the two faster ones:
 *
 *   version  | cycle  | perf | interrupts | E03    | F04    || FUL4G
 *   ---------+--------+------+------------+--------+--------++-------
 *   UCE 466  | 6 usec | MIN  | no         | /      | PONT2N ||   0
 *   UCE 467  | 4 usec | MAX  | no         | PONT2P | PONT2P ||   1
 *   UCE 467  | 4 usec | MAX  | YES        | PONT2P | /      ||   1
 *   UCE 468  | 2 usec | MAX  | no         | PONT2N | PONT2P ||   1
 *   UCE 468  | 2 usec | MAX  | YES        | PONT2N | /      ||   1
 *
 * FUL4G reads "this machine has the MAX instruction set", and it is low for
 * exactly ONE strap: F04 = PONT2N, the 6 usec UCE 466.  An EMPTY F04 is the
 * interrupts-enabled variant of the two fast models, so it gives FUL4G = 1 --
 * which is why this tests for PONT2N rather than for PONT2P.  (It did test
 * for PONT2P, which read the table off the "no interrupts" rows only and got
 * an empty F04 backwards.) */
SIG(FUL4G) { return ge->options.F04 != PONT_2N; }
 
/* The note on ch.002: FUL01/FUL11/FUL4F follow FEL06/FEL16/FUL4G unless the
 * maintenance panel's S42 "LAMPS" switch is in position DIAG, in which case
 * they become 0 / 0 / 1 regardless of the straps. FUL4F is the form the
 * timing charts cite as {FUL4}. */
SIG(FUL4F) { return ge->options.S42_diag ? 1 : FUL4G(ge); }
 
/* Names the charts and the older transcriptions use. */
SIG(FUL2) { return FUL26(ge); }
SIG(FUL3) { return FUL36(ge); }
SIG(FUL4) { return FUL4F(ge); }
 
/* Entry inverters, gates 22/26/31.  Each is a NAND with both inputs tied to
 * one net, which is how this drawing draws an inverter. */
SIG(CI451) { return ge->ua_controls.logic; }
SIG(CI461) { return ge->ua_controls.decimal_and; }
SIG(CI471) { return ge->ua_controls.subtract_xor; }
SIG(CI45D) { return !CI451(ge); }
SIG(CI46B) { return !CI461(ge); }
SIG(CI47B) { return !CI471(ge); }
 
SIG(UCOA1) { return !(CI46B(ge) && CI47B(ge)); }              /* gate 32 */
SIG(UCO21) { return !(CI45D(ge) && UCOA1(ge)); }              /* gate 33 */
SIG(UCO2A) { return !UCO21(ge); }                             /* gate 34 */
SIG(UCO4A) { return !(CI451(ge) && CI471(ge)); }              /* gate 23 */
SIG(UCO41) { return !UCO4A(ge); }                             /* gate 24 */
SIG(UCO0A) { return !(CI45D(ge) && CI461(ge) && CI47B(ge)); } /* gate 27 */
SIG(UCO01) { return !UCO0A(ge); }                       /* gates 25 + 28 */
SIG(UCO1A) { return !(CI45D(ge) && CI471(ge)); }              /* gate 29 */
SIG(UCO11) { return !UCO1A(ge); }                             /* gate 30 */
 
/* CI50's effect, cp06 ch.094 gates 8/9/12: CI50B = /CI501 is an input of the
 * UZE71 and UZE81 NANDs, so raising CI50 forces both zone enables inactive. */
SIG(CI50B) { return !ge->ua_controls.low_zone_only; }
SIG(UZE71_enabled) { return CI50B(ge); }
SIG(UZE81_enabled) { return CI50B(ge); }
 
SIG(DO07A) { return !(!BIT(ge->rFO, 0) && !BIT(ge->rFO, 6) && DO041(ge)); }
SIG(DO071) { return !DO07A(ge); }
 
/* Function classes DO00 and DO06, cp06 ch.229 "FUNCTION DECODING" (dwg
 * 14013 0650).  Both gates take their inputs on unlabelled bus lines, read
 * off the sheet rather than inferred: gate 10 pin 1 and gate 4 pin 1 both
 * come from margin stub (105-8) C38-12 = FO06F, gate 4 pin 4 from (104-16)
 * D38-03 = FO036, and gate 4 pin 5 from U07 pin 6 = DO041.
 *
 * Together with DO01 (jumps) and DO02 (LA) these are the four classes whose
 * beta-band ANDs feed CU01 -- see docs/transcriptions/cu01-partial-command.md.
 * The partition they produce is exact over the whole ISA: DO00 takes the
 * console/control codes at 0x02/0x07/0x0A, DO06 takes LPSR alone, and every
 * family that continues into the executive band falls outside all four. */
SIG(DO00A) { return !(!BIT(ge->rFO, 7) && !BIT(ge->rFO, 6)); }
SIG(DO001) { return !DO00A(ge); }
SIG(DO06A) {
    return !(!BIT(ge->rFO, 6) && BIT(ge->rFO, 3) && BIT(ge->rFO, 0) &&
             DO041(ge));
}
SIG(DO061) { return !DO06A(ge); }
 
/* Function-class AND beta-band terms, cp06 ch.248 "FUNCTION AND STATUS CODES
 * ANDS" (gates 9, 8, 4) and ch.243 gate 5.  All four have the same shape --
 * one function class ANDed with the beta-state decode -- and all four are
 * leaves of the CU01 partial command, CM011 below.
 *
 * DE00A used to be stubbed to a constant with the note "doesn't work for
 * nop/lon/loff ecc".  It was transcribed correctly all along; what was
 * missing were its three siblings, so the one leaf was being asked to carry
 * the whole condition and could only do it by being forced true. */
SIG(DE00A) { return !(DO011(ge) && DI062(ge)); }   /* jumps + JRT   ch.248-9 */
SIG(DE06A) { return !(DO021(ge) && DI062(ge)); }   /* LA            ch.248-8 */
SIG(DE11A) { return !(DI061(ge) && DO001(ge)); }   /* console group ch.248-4 */
SIG(DE13A) { return !(DO061(ge) && DI061(ge)); }   /* LPSR          ch.243-5 */
SIG(DE001) { return !DE00A(ge); }
 
/* CU01's partial command, cp06 ch.252-7 "PARTIAL COMMANDS GENERATION": a
 * four-input NAND over the active-low leaves above, i.e. the command asserts
 * when ANY class claims the opcode.  CM01A (ch.252-10) is its inverse; the
 * timing charts cite the active-high call CM01A0. */
SIG(CM011) {
    return !(DE00A(ge) && DE06A(ge) && DE11A(ge) && DE13A(ge));
}
SIG(CM01A) { return !CM011(ge); }
SIG(CM01A0) { return !CM01A(ge); }
 
SIG(DE07A) { return !(DO071(ge) && DI062(ge)); }
SIG(DE23A) { return !(DE001(ge) && BIT(ge->rFO, 4) && BIT(ge->rL1, 5)); }
SIG(DE231) { return !(DE23A(ge) && DE23A(ge)); }
 
SIG(DA25A) { return !(DI111(ge) && DO021(ge)); }
 
SIG(PC011); SIG(PC111); SIG(PC211);
SIG(DU161) { return !(BIT(ge->rSA, 1) && PC111(ge) && PC211(ge) && PC111(ge)); }
SIG(DU18A) { return !(ge->RIG3 && BIT(ge->rL2, 7)); }
SIG(DU19A) { return !(ge->RIG1 && PC011(ge) && !ge->RACI); }
SIG(DU201) { return !(DU18A(ge) && DU19A(ge)); }
SIG(EC56A) { return !(DI201(ge) && BIT(ge->rL2, 7)); }
SIG(EC69A) { return !(AF41(ge) && DI572(ge));}
SIG(EC70A) { return !(AF51(ge) && DI572(ge)); }
SIG(ED70A) { return !(!ge->AINI && DI971(ge)); }
SIG(ED75A) { return !(ge->AINI && DI011(ge) && DI291(ge)); }
SIG(ED79A) { return !(DI291(ge) && DU161(ge) && BIT(ge->rSA, 0)); }
SIG(ED91A) { return !(DE231(ge) && DU201(ge)); }
 
SIG(DE00A0) { return !DE00A(ge); }
SIG(DE07A0) { return !DE07A(ge); }
SIG(DE08A0) { return !(!BIT(ge->rFO, 1) && DI062(ge) && DO071(ge)); }
 
SIG(DA25A0) { return !DA25A(ge); }
SIG(DI11A0) { return !DI11A(ge); }
SIG(DI12A0) { return !DI12A(ge); }
SIG(DI13A0) { return !DI13A(ge); }
SIG(DI17A0) { return !DI17A(ge); }
SIG(DI18A0) { return !DI18A(ge); }
SIG(DI18B0) { return !DI18B(ge); }
SIG(DI19A0) { return !DI19A(ge); }
SIG(DI20A0) { return !DI20A(ge); }
SIG(DI21A0) { return !DI21A(ge); }
SIG(DI22A0) { return !DI22A(ge); }
SIG(DI24A0) { return !DI24A(ge); }
SIG(DI25A0) { return !DI25A(ge); }
SIG(DI28A0) { return !DI28A(ge); }
SIG(DI28B0) { return !DI28B(ge); }
SIG(DI29A0) { return !DI29A(ge); }
SIG(DI57A0) { return !DI57A(ge); }
SIG(DI57B0) { return !DI57B(ge); }
/* DI60A: the ch.239 sheet (foglio 217) is PHYSICALLY MISSING from the cp06
 * scan (audit round-2: p298=ch238 -> p299=ch240, and ch256 is bound twice at
 * p315/316). Equation reconstructed from fan-out callouts on surviving
 * sheets: DI60A = NAND(DI121 [252-11], SA028 [256-4]) — i.e. the E4|E5|E6|E7
 * band decode. Within the only states that use DI60A0 (E4/E5/E6/E7) it is
 * identically 1, matching the previous stub. Medium confidence (callout
 * reconstruction; the generating sheet itself is unscanned). */
SIG(DI60A) { return !(DI121(ge) && BIT(ge->rSA, 2)); }
SIG(DI60A0) { return !DI60A(ge); }
SIG(DI64A0) { return !DI64A(ge); }
SIG(DI65A0) { return !DI65A(ge); }
SIG(DI66A0) { return !DI66A(ge); }
SIG(DI67A0) { return !DI67A(ge); }
SIG(DI79A0) { return !DI79A(ge); }
SIG(DI82A0) { return !DI82A(ge); }
SIG(DI83A0) { return !DI83A(ge); }
SIG(DI84A0) { return !DI84A(ge); }
SIG(DI85A0) { return !DI85A(ge); }
SIG(DI86A0) { return !DI86A(ge); }
SIG(DI87A0) { return !DI87A(ge); }
SIG(DI91A0) { return !DI91A(ge); }
SIG(DI93A0) { return !DI93A(ge); }
SIG(DI94A0) { return !DI94A(ge); }
SIG(DI95A0) { return !DI95A(ge); }
SIG(DI97A0) { return !DI97A(ge); }
 
SIG(EC56A0) { return !EC56A(ge); }
SIG(EC69A0) { return !EC69A(ge); }
SIG(EC70A0) { return !EC70A(ge); }
SIG(ED70A0) { return !ED70A(ge); }
SIG(ED75A0) { return !ED75A(ge); }
SIG(ED79A0) { return !ED79A(ge); }
SIG(ED91A0) { return !ED91A(ge); }
 
/* MC */
SIG(AITE)  { return ge->console_switches.SITE; }
SIG(AITEA) { return !AITE(ge); }
 
/* RI — integrated card reader on channel 1 (COCA pins; see docs/signals/01-coca-connector.md). */
SIG(LU081) { return reader_get_LU08(ge); }       /* LU08N : char-ready strobe   */
SIG(LUPO1) { return reader_get_LUPO1(ge); }      /* LUPOR : reader free / ready */
SIG(FINI1) { return reader_get_FINI1(ge); }      /* FININ : end-of-read         */
SIG(FIDE1) { return ge->integrated_reader.fiden; }  /* FIDEN: end-of-sequence   */
SIG(LURE1) { return ge->integrated_reader.luren; }  /* LUREN: error / jam       */
SIG(LUSE1) { return ge->integrated_reader.lusen; }  /* LUSEN: out-of-service    */
SIG(LENO1) { return ge->integrated_reader.lenon; }  /* LENON: not operable      */
SIG(BI201) { return ge->integrated_reader.bi20;  }  /* BI20 : binary 2nd-nibble */
SIG(POM01) { return ge->integrated_reader.pom01; }  /* POM01: binary-mode indic */
SIG(PICO1) { return ge->integrated_reader.picon; }  /* PICON: first-column      */
 
/* RL1U1: channel-1 read-length L1 "all ones" (terminal-count) decode (CPU
 * signal index ch.128). A length-counted channel-1 transfer ends at L1+1
 * characters; counting L1 down per character, the terminal is reached when L1
 * underflows to all ones. Pure decode of rL1, so it is exposed here and reused
 * by the RENIA end-of-transfer equation in msl-states.c. */
SIG(RL1U1) { return (ge->rL1 & 0xff) == 0xff; }
 
/* PI */
SIG(FUSE1) { return 0; }
SIG(FINA1) { return 0; }
 
/* ST3 */
SIG(MARE3) { return connector_get_MARE(&ge->ST3); }
SIG(TE103) { return connector_get_TE10(&ge->ST3); }
SIG(TE203) { return connector_get_TE20(&ge->ST3); }
SIG(TE303) { return connector_get_TE30(&ge->ST3); }
SIG(FINE3) { return connector_get_FINE(&ge->ST3); }
 
/* ST4 */
SIG(MARE4) { return connector_get_MARE(&ge->ST4); }
SIG(TE104) { return connector_get_TE10(&ge->ST4); }
SIG(TE204) { return connector_get_TE20(&ge->ST4); }
SIG(TE304) { return connector_get_TE30(&ge->ST4); }
SIG(FINE4) { return connector_get_FINE(&ge->ST4); }
 
SIG(PC111); SIG(PC131); SIG(PC141); SIG(PC121);
 
SIG(PB11A) { return !(FINA1(ge) && PC111(ge)); }
SIG(PB13A) { return !(TE303(ge) && PC131(ge)); }
SIG(PB14A) { return !(TE304(ge) && PC141(ge)); }
 
SIG(RT121) { /* UNIV 1.2µs */ return ge->RT121; }
SIG(RT131) { /* UNIV 1.2µs */ return ge->RT131; }
 
SIG(RB101) { return !(AITEA(ge) && PB11A(ge) && PB13A(ge) && PB14A(ge)); }
SIG(RB121) { /* UNIV 1.2µs */ return RB101(ge); }
SIG(RB12A) { return !RB121(ge); }
SIG(RB01A) { return !(RT121(ge) && RB101(ge)); }
SIG(RB111) { return !(RB12A(ge) && RB01A(ge)); }
 
SIG(PF12A) { return !(FINI1(ge) && PC121(ge)); }
SIG(PF13A) { return !(FINE3(ge) && PC131(ge)); }
SIG(PF14A) { return !(FINE4(ge) && PC141(ge)); }
SIG(RF101) { return !(PF12A(ge) && PF13A(ge) && PF14A(ge)); }
 
SIG(PC11A); SIG(PC12A); SIG(PC13A); SIG(PC14A);
 
SIG(PC111) { return !PC11A(ge); };
SIG(PC121) { return !PC12A(ge); };
SIG(PC131) { return !PC13A(ge); };
SIG(PC141) { return !PC14A(ge); };
 
SIG(RUF11) { return  ge->RUF1; }
SIG(RUF1A) { return !ge->RUF1; }
SIG(RASI1) { return  ge->RASI; }
SIG(TO501) { return ge->current_clock == TO50; }
 
SIG(PELEA) { return !(LU081(ge) && LUPO1(ge)); }
SIG(RELO1) { return !(PELEA(ge) && RUF1A(ge)); }
SIG(PAM4A) { return !(RELO1(ge) && RASI1(ge) && PC121(ge)); }
SIG(PM11A) { return !(FUSE1(ge) && PC111(ge)); }
SIG(PM13A) { return !(MARE3(ge) && PC131(ge)); }
SIG(PM14A) { return !(MARE4(ge) && PC141(ge)); }
SIG(RM101) { return !(PM11A(ge) && PM13A(ge) && PM14A(ge)); }
SIG(PAM1A) { return !(RASI1(ge) && RM101(ge)); }
SIG(RS011) { return !(PAM4A(ge) && PAM1A(ge)); }
SIG(PIM1A) { return !(TO501(ge) || RS011(ge) || RB111(ge) || RUF11(ge)); }
SIG(PIM11) { return !PIM1A(ge); }
SIG(PIC1A) { return !ge->PIC1; }
SIG(PUC11) { return !(PIC1A(ge) && PIM1A(ge)); }
SIG(PUC1)  { return PUC11(ge); }
 
/* !(channel 2 non overlap) */
SIG(PC01A) { return !(!BIT(ge->rL2, 3) && !BIT(ge->rL2, 0)); }
SIG(PC011) { return !PC01A(ge); }
 
/* !(channel2 overlapped) */
SIG(PC03A) { return !(!BIT(ge->rL2, 0) && BIT(ge->rL2, 3)); }
SIG(PC031) { return !PC03A(ge); }
 
SIG(PUC26) { return ge->PUC2; }
SIG(PUC36) { return ge->PUC3; }
 
SIG(PB061)    { return  ge->PB06; }
SIG(PB06A)    { return !ge->PB06; }
SIG(PB071)    { return  ge->PB07; }
SIG(PB07A)    { return !ge->PB07; }
SIG(PB261)    { return  ge->PB26; }
SIG(PB26A)    { return !ge->PB26; }
SIG(PB361)    { return  ge->PB36; }
SIG(PB36A)    { return !ge->PB36; }
SIG(PB371)    { return  ge->PB37; }
SIG(PB37A)    { return !ge->PB37; }
SIG(PUC21)    { return  ge->PUC2; }
SIG(PUC2A)    { return !ge->PUC2; }
SIG(PUC31)    { return  ge->PUC3; }
SIG(PUC3A)    { return !ge->PUC3; }
 
SIG(PC11A)    { return !(PUC11(ge) && PB071(ge) && PB061(ge)); }
SIG(PC12A)    { return !(PUC11(ge) && PB071(ge) && PB06A(ge)); }
SIG(PC13A)    { return !(PUC11(ge) && PB07A(ge) && PB06A(ge)); }
SIG(PC14A)    { return !(PUC11(ge) && PB07A(ge) && PB061(ge)); }
SIG(PC21A)    { return !(PUC21(ge) && PB261(ge)); }
SIG(PC22A)    { return !(PUC21(ge) && PB26A(ge)); }
SIG(PC31A)    { return !(PUC31(ge) && PB371(ge) && PB361(ge)); }
SIG(PC32A)    { return !(PUC31(ge) && PB371(ge) && PB36A(ge)); }
SIG(PC33A)    { return !(PUC31(ge) && PB37A(ge) && PB36A(ge)); }
SIG(PC34A)    { return !(PUC31(ge) && PB37A(ge) && PB361(ge)); }
 
SIG(SEPEI)    { return !(PC11A(ge) && PC21A(ge) && PC31A(ge)); }
SIG(PU002)    { return !(PC12A(ge) && PC22A(ge) && PC32A(ge)); }
SIG(PU003)    { return !(PC13A(ge) && PC33A(ge)); }
SIG(PU004)    { return !(PC14A(ge) && PC34A(ge)); }
 
SIG(PUB01_d1) { return !(SEPEI(ge) && BIT(ge->rL1, 7) && BIT(ge->rL1, 6)); }
SIG(PUB01_d2) { return !(PU002(ge) && BIT(ge->rL1, 7) && BIT(ge->rL1, 6)); }
SIG(PUB01_d3) { return !(PU003(ge) && BIT(ge->rL1, 7) && BIT(ge->rL1, 6)); }
SIG(PUB01_d4) { return !(PU004(ge) && BIT(ge->rL1, 7) && BIT(ge->rL1, 6)); }
 
SIG(PUB01)    { return !(PUB01_d1(ge) && PUB01_d2(ge) && PUB01_d3(ge) && PUB01_d4(ge)); }
 
SIG(PC211)    { return !PC21A(ge); }
 
SIG(PC321)    { return !PC32A(ge); }
SIG(PC331)    { return !PC33A(ge); }
SIG(PC341)    { return !PC34A(ge); }
 
/* !(!rejected && in transfer) => rejected || !in_transfer */
SIG(DU871) { return !(!ge->RACI && ge->RASI); }
/* for state b8, FA is set if L200 && L203, which is channel 2 in overlap */
/* !(channel2 in overlap && channel2 in transfer */
SIG(DU881) { return !(BIT(ge->ffFA, 2) && ge->PUC2); }
 
SIG(DU89A) { return !(DU871(ge) && DU881(ge) && PC011(ge) && DU881(ge)); }
 
SIG(DU90A) { return !(PUC26(ge) && !BIT(ge->rRO, 0)); }
SIG(DU91A) { return !(BIT(ge->rRO, 0) && !BIT(ge->rRO, 3) && PUC36(ge)); }
 
SIG(DU92)  { return !(DU90A(ge) && DU91A(ge)); }
 
SIG(DU93A) { return !(BIT(ge->rL2, 7) && BIT(ge->rL2, 5)); }
 
SIG(DU93)  { return !DU93A(ge); }
 
SIG(DU95A) { return !(!BIT(ge->rRO, 1) && !BIT(ge->rRO, 2) && BIT(ge->rRO, 6)); }
SIG(DU95) { return !DU95A(ge); }
 
SIG(DU96A) { return !(BIT(ge->rL2, 7) && BIT(ge->rL2, 7)); }
SIG(DU96) { return !DU96A(ge); }
 
SIG(DU97A) { return !(ge->PUC2 ^
                      BIT(ge->rL2, 0) ^
                      BIT(ge->rL2, 0) ^
                      BIT(ge->rL2, 3)); }
 
SIG(DU97) { return !DU97A(ge); }
 
SIG(DU98) { return !(DU89A(ge) && PC03A(ge)); }
 
/* RI outgoing */
SIG(TU00A) { return !(RT121(ge) && RUF1A(ge) && PC121(ge));}
 
SIG(FU091) { return 0; } /* todo: printer */
 
SIG(PTA3A) { return !(TE103(ge) && TE203(ge)); }
SIG(PTA31) { return !PTA3A(ge); }
 
SIG(PTA4A) { return !(TE104(ge) && TE204(ge)); }
SIG(PTA41) { return !PTA4A(ge); }
 
SIG(PA11A) { return !(FU091(ge) && PC111(ge)); }
SIG(PA12A) { return !(LU081(ge) && PC121(ge)); }
SIG(PA13A) { return !(PTA31(ge) && PC131(ge)); }
SIG(PA14A) { return !(PTA41(ge) && PC141(ge)); }
SIG(RA101) { return !(PA11A(ge) && PA12A(ge) && PA13A(ge) && PA13A(ge) && PA14A(ge)); }
 
/* } */
 
/* Channel-2 reader-input selection (Phase 4). These gate PIB21 = enable NE input
 * from connector 2 on a channel-2 cycle, mirroring the channel-1 path
 * PB12A = !(RESI1 . PC121):
 *   PB22A = !(RET21 . PC221), so the channel-2 reader read latches NE->RO when
 *   the channel-2 cycle is active (RET21) AND connector 2 is selected on channel
 *   2 (PC221). RET21 is the channel-2 sync request RIA2 (mirror of RESI1 for ch-1).
 *   PC221 = !PC22A = PUC21 . ~PB26 (channel-2 unit selected, connector selector
 *   PB26=0 => connector 2). Both were stubbed to 0, which left the integrated
 *   reader selectable only on channel 1 (via PB12A); these light the channel-2
 *   path. Off for channel-1 ops (RIA2=0 / PUC2=0), so the channel-1 bootstrap is
 *   unaffected. */
/* RET21: channel-2 cycle-assignment memory, the T010-clocked latch of RES2
 * (cp06 ch.132-6, verified on the sheet: RET21 = /((RES2A·T0107)+(T010C·RET2A))).
 * Was approximated as raw RIA2, which ignored the priority masking in RES2
 * (ch.1/ch.3 contention) and the latching. */
SIG(RET21) { return ge->RET2; }
SIG(PC221) { return !PC22A(ge); }
 
SIG(PIB1A) { return !(RET21(ge) && PC211(ge)); }
SIG(PIB11) { return !PIB1A(ge); }
 
SIG(PB12A) { return !(RESI1(ge) && PC121(ge)); }
SIG(PB22A) { return !(RET21(ge) && PC221(ge)); }
SIG(PB32A) { return !(RES31(ge) && PC321(ge)); }
SIG(PIB21) { return !(PB12A(ge) && PB22A(ge) && PB32A(ge)); }
 
SIG(RB13A) { return !(RESI1(ge) && PC131(ge)); }
SIG(RB33A) { return !(RES31(ge) && PC331(ge)); }
SIG(PIB31) { return !(RB13A(ge) && RB33A(ge)); }
 
SIG(RB14A) { return !(RESI1(ge) && PC141(ge)); }
SIG(RB34A) { return !(RES31(ge) && PC341(ge)); }
SIG(PIB41) { return !(RB14A(ge) && RB34A(ge)); }
 
static inline uint16_t NE_knot(struct ge *ge) {
    uint16_t ret = 0;
    const char *where = "";
 
    uint8_t count = PIB11(ge) + PIB21(ge) + PIB31(ge) + PIB41(ge);
 
    if (count > 1) {
        ge_log(LOG_PERI, "multiple input signals for NE knot (?!)\n");
    }
 
    if (PIB11(ge)) {
        where = "PI";
        ge_log(LOG_PERI, "TODO -- printer\n");
    }
 
    if (PIB21(ge)) {
        where = "RI";
        ret = ge->integrated_reader.data;
    }
 
    if (PIB31(ge)) {
        where = "ST3";
        ret = ge->ST3.data;
    }
 
    if (PIB41(ge)) {
        where = "ST4";
        ret = ge->ST4.data;
    }
 
    ge_log(LOG_PERI, "READING FROM NE KNOT %s --> %03x\n", where, ret);
    return ret;
}
 
/* } */
 
#define NAOR(a, b, c, d) !(a || b || c || d)
 
SIG(RT111) { return 0; }
 
SIG(RT311) { return 0; }
SIG(RT321) { return 0; }
SIG(RT331) { return 0; }
 
SIG(RATE1) { return 0; }
SIG(PUOO3) { return 0; }
SIG(RUF31) { return 0; }
SIG(RAVI1) { return 0; }
 
SIG(TU10C) { return NAOR(RT111(ge), PC131(ge), RT311(ge), PC331(ge)); }
SIG(TU20C) { return NAOR(RT121(ge), PC131(ge), RT321(ge), PC331(ge)); }
SIG(TU30C) { return NAOR(RT131(ge), PC131(ge), RT331(ge), PC331(ge)); }
SIG(AEBEC) { return !(RATE1(ge) && PC131(ge)); }
SIG(AECO3) { return !PUOO3(ge); }
SIG(FINUC) { return NAOR(RUF11(ge), PC131(ge), RUF31(ge), PC331(ge)); }
SIG(PV13A) { return !(RAVI1(ge) && PC131(ge)); }
SIG(VICU3) { return !(FINUC(ge) && PV13A(ge)); }
/* } */
 
#endif